Lines Matching refs:iova
205 * The IOMMU HW may support 16GB iova. In order to balance the IOVA ranges,
206 * different masters will be put in different iova ranges, for example vcodec
210 * Here list the iova ranges this SoC supports and which larbs/ports are in
213 * 16GB iova all use one pgtable, but each a region is a iommu group.
308 #define MTK_IOMMU_TLB_ADDR(iova) ({ \
309 dma_addr_t _addr = iova; \
389 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
431 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A);
432 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
511 "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n",
646 /* Share pgtable when 2 MM IOMMU share the pgtable or one IOMMU use multiple iova ranges */
683 /* Update the iova region for this domain */
779 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
790 return dom->iop->map_pages(dom->iop, iova, paddr, pgsize, pgcount, prot, gfp, mapped);
794 unsigned long iova, size_t pgsize, size_t pgcount,
799 iommu_iotlb_gather_add_range(gather, iova, pgsize * pgcount);
800 return dom->iop->unmap_pages(dom->iop, iova, pgsize, pgcount, gather);
820 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
825 mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank);
829 dma_addr_t iova)
834 pa = dom->iop->iova_to_phys(dom->iop, iova);
908 * Otherwise, each iova region is a iommu group/domain.