Lines Matching defs:regval
461 u32 int_state, regval, va34_32, pa34_32;
470 regval = readl_relaxed(base + REG_MMU0_INT_ID);
474 regval = readl_relaxed(base + REG_MMU1_INT_ID);
490 fault_larb = F_MMU_INT_ID_COMM_ID(regval);
491 sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
492 fault_port = F_MMU_INT_ID_PORT_ID(regval);
494 fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
495 sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
496 fault_port = F_MMU_INT_ID_PORT_ID(regval);
498 fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval);
499 fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval);
501 fault_port = F_MMU_INT_ID_PORT_ID(regval);
502 fault_larb = F_MMU_INT_ID_LARB_ID(regval);
512 int_state, fault_iova, fault_pa, regval, fault_larb, fault_port,
517 regval = readl_relaxed(base + REG_MMU_INT_CONTROL0);
518 regval |= F_INT_CLR_BIT;
519 writel_relaxed(regval, base + REG_MMU_INT_CONTROL0);
1022 u32 regval;
1029 regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
1032 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG);
1033 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
1035 writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);
1043 regval = F_MMU_VLD_PA_RNG(7, 4);
1044 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG);
1053 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL);
1054 regval &= ~F_MMU_WR_THROT_DIS_MASK;
1055 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL);
1060 regval = 0;
1062 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL);
1064 regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
1066 regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
1068 writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);
1071 regval = F_L2_MULIT_HIT_EN |
1077 writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0);
1079 regval = F_INT_TRANSLATION_FAULT |
1086 writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL);
1089 regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
1091 regval = lower_32_bits(data->protect_base) |
1093 writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR);