Lines Matching refs:iommu
18 #include <linux/iommu.h>
54 static int __enable_clocks(struct msm_iommu_dev *iommu)
58 ret = clk_enable(iommu->pclk);
62 if (iommu->clk) {
63 ret = clk_enable(iommu->clk);
65 clk_disable(iommu->pclk);
71 static void __disable_clocks(struct msm_iommu_dev *iommu)
73 if (iommu->clk)
74 clk_disable(iommu->clk);
75 clk_disable(iommu->pclk);
120 struct msm_iommu_dev *iommu = NULL;
124 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
125 ret = __enable_clocks(iommu);
129 list_for_each_entry(master, &iommu->ctx_list, list)
130 SET_CTX_TLBIALL(iommu->base, master->num, 0);
132 __disable_clocks(iommu);
142 struct msm_iommu_dev *iommu = NULL;
147 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
148 ret = __enable_clocks(iommu);
152 list_for_each_entry(master, &iommu->ctx_list, list) {
156 iova |= GET_CONTEXTIDR_ASID(iommu->base,
158 SET_TLBIVA(iommu->base, master->num, iova);
163 __disable_clocks(iommu);
206 static void config_mids(struct msm_iommu_dev *iommu,
215 SET_M2VCBR_N(iommu->base, mid, 0);
216 SET_CBACR_N(iommu->base, ctx, 0);
219 SET_VMID(iommu->base, mid, 0);
222 SET_CBNDX(iommu->base, mid, ctx);
225 SET_CBVMID(iommu->base, ctx, 0);
228 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);
231 SET_NSCFG(iommu->base, mid, 3);
366 struct msm_iommu_dev *iommu, *ret = NULL;
369 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
370 master = list_first_entry(&iommu->ctx_list,
374 ret = iommu;
384 struct msm_iommu_dev *iommu;
388 iommu = find_iommu_for_dev(dev);
391 if (!iommu)
394 return &iommu->iommu;
401 struct msm_iommu_dev *iommu;
409 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
410 master = list_first_entry(&iommu->ctx_list,
414 ret = __enable_clocks(iommu);
418 list_for_each_entry(master, &iommu->ctx_list, list) {
425 msm_iommu_alloc_ctx(iommu->context_map,
426 0, iommu->ncb);
431 config_mids(iommu, master);
432 __program_context(iommu->base, master->num,
435 __disable_clocks(iommu);
436 list_add(&iommu->dom_node, &priv->list_attached);
451 struct msm_iommu_dev *iommu;
458 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
459 ret = __enable_clocks(iommu);
463 list_for_each_entry(master, &iommu->ctx_list, list) {
464 msm_iommu_free_ctx(iommu->context_map, master->num);
465 __reset_context(iommu->base, master->num);
467 __disable_clocks(iommu);
516 struct msm_iommu_dev *iommu;
525 iommu = list_first_entry(&priv->list_attached,
528 if (list_empty(&iommu->ctx_list))
531 master = list_first_entry(&iommu->ctx_list,
536 ret = __enable_clocks(iommu);
541 SET_CTX_TLBIALL(iommu->base, master->num, 0);
542 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);
544 par = GET_PAR(iommu->base, master->num);
547 if (GET_NOFAULT_SS(iommu->base, master->num))
552 if (GET_FAULT(iommu->base, master->num))
555 __disable_clocks(iommu);
587 struct msm_iommu_dev **iommu,
593 if (list_empty(&(*iommu)->ctx_list)) {
600 list_add(&master->list, &(*iommu)->ctx_list);
618 struct msm_iommu_dev *iommu = NULL, *iter;
625 iommu = iter;
630 if (!iommu) {
635 ret = insert_iommu_master(dev, &iommu, spec);
644 struct msm_iommu_dev *iommu = dev_id;
650 if (!iommu) {
656 pr_err("base = %08x\n", (unsigned int)iommu->base);
658 ret = __enable_clocks(iommu);
662 for (i = 0; i < iommu->ncb; i++) {
663 fsr = GET_FSR(iommu->base, i);
667 print_ctx_regs(iommu->base, i);
668 SET_FSR(iommu->base, i, 0x4000000F);
671 __disable_clocks(iommu);
691 * taken care when the iommu client does a writel before
705 struct msm_iommu_dev *iommu;
708 iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
709 if (!iommu)
712 iommu->dev = &pdev->dev;
713 INIT_LIST_HEAD(&iommu->ctx_list);
715 iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk");
716 if (IS_ERR(iommu->pclk))
717 return dev_err_probe(iommu->dev, PTR_ERR(iommu->pclk),
720 ret = clk_prepare(iommu->pclk);
722 return dev_err_probe(iommu->dev, ret,
725 iommu->clk = devm_clk_get(iommu->dev, "iommu_clk");
726 if (IS_ERR(iommu->clk)) {
727 clk_unprepare(iommu->pclk);
728 return dev_err_probe(iommu->dev, PTR_ERR(iommu->clk),
732 ret = clk_prepare(iommu->clk);
734 clk_unprepare(iommu->pclk);
735 return dev_err_probe(iommu->dev, ret, "could not prepare iommu_clk\n");
739 iommu->base = devm_ioremap_resource(iommu->dev, r);
740 if (IS_ERR(iommu->base)) {
741 ret = dev_err_probe(iommu->dev, PTR_ERR(iommu->base), "could not get iommu base\n");
746 iommu->irq = platform_get_irq(pdev, 0);
747 if (iommu->irq < 0) {
752 ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);
754 dev_err(iommu->dev, "could not get ncb\n");
757 iommu->ncb = val;
759 msm_iommu_reset(iommu->base, iommu->ncb);
760 SET_M(iommu->base, 0, 1);
761 SET_PAR(iommu->base, 0, 0);
762 SET_V2PCFG(iommu->base, 0, 1);
763 SET_V2PPR(iommu->base, 0, 0);
764 par = GET_PAR(iommu->base, 0);
765 SET_V2PCFG(iommu->base, 0, 0);
766 SET_M(iommu->base, 0, 0);
774 ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,
778 iommu);
780 pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);
784 list_add(&iommu->dev_node, &qcom_iommu_devices);
786 ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL,
793 ret = iommu_device_register(&iommu->iommu, &msm_iommu_ops, &pdev->dev);
800 iommu->base, iommu->irq, iommu->ncb);
804 clk_unprepare(iommu->clk);
805 clk_unprepare(iommu->pclk);
810 { .compatible = "qcom,apq8064-iommu" },
816 struct msm_iommu_dev *iommu = platform_get_drvdata(pdev);
818 clk_unprepare(iommu->clk);
819 clk_unprepare(iommu->pclk);