Lines Matching refs:base
78 static void msm_iommu_reset(void __iomem *base, int ncb)
82 SET_RPUE(base, 0);
83 SET_RPUEIE(base, 0);
84 SET_ESRRESTORE(base, 0);
85 SET_TBE(base, 0);
86 SET_CR(base, 0);
87 SET_SPDMBE(base, 0);
88 SET_TESTBUSCR(base, 0);
89 SET_TLBRSW(base, 0);
90 SET_GLOBAL_TLBIALL(base, 0);
91 SET_RPU_ACR(base, 0);
92 SET_TLBLKCRWE(base, 1);
95 SET_BPRCOSH(base, ctx, 0);
96 SET_BPRCISH(base, ctx, 0);
97 SET_BPRCNSH(base, ctx, 0);
98 SET_BPSHCFG(base, ctx, 0);
99 SET_BPMTCFG(base, ctx, 0);
100 SET_ACTLR(base, ctx, 0);
101 SET_SCTLR(base, ctx, 0);
102 SET_FSRRESTORE(base, ctx, 0);
103 SET_TTBR0(base, ctx, 0);
104 SET_TTBR1(base, ctx, 0);
105 SET_TTBCR(base, ctx, 0);
106 SET_BFBCR(base, ctx, 0);
107 SET_PAR(base, ctx, 0);
108 SET_FAR(base, ctx, 0);
109 SET_CTX_TLBIALL(base, ctx, 0);
110 SET_TLBFLPTER(base, ctx, 0);
111 SET_TLBSLPTER(base, ctx, 0);
112 SET_TLBLKCR(base, ctx, 0);
113 SET_CONTEXTIDR(base, ctx, 0);
130 SET_CTX_TLBIALL(iommu->base, master->num, 0);
156 iova |= GET_CONTEXTIDR_ASID(iommu->base,
158 SET_TLBIVA(iommu->base, master->num, iova);
215 SET_M2VCBR_N(iommu->base, mid, 0);
216 SET_CBACR_N(iommu->base, ctx, 0);
219 SET_VMID(iommu->base, mid, 0);
222 SET_CBNDX(iommu->base, mid, ctx);
225 SET_CBVMID(iommu->base, ctx, 0);
228 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);
231 SET_NSCFG(iommu->base, mid, 3);
235 static void __reset_context(void __iomem *base, int ctx)
237 SET_BPRCOSH(base, ctx, 0);
238 SET_BPRCISH(base, ctx, 0);
239 SET_BPRCNSH(base, ctx, 0);
240 SET_BPSHCFG(base, ctx, 0);
241 SET_BPMTCFG(base, ctx, 0);
242 SET_ACTLR(base, ctx, 0);
243 SET_SCTLR(base, ctx, 0);
244 SET_FSRRESTORE(base, ctx, 0);
245 SET_TTBR0(base, ctx, 0);
246 SET_TTBR1(base, ctx, 0);
247 SET_TTBCR(base, ctx, 0);
248 SET_BFBCR(base, ctx, 0);
249 SET_PAR(base, ctx, 0);
250 SET_FAR(base, ctx, 0);
251 SET_CTX_TLBIALL(base, ctx, 0);
252 SET_TLBFLPTER(base, ctx, 0);
253 SET_TLBSLPTER(base, ctx, 0);
254 SET_TLBLKCR(base, ctx, 0);
257 static void __program_context(void __iomem *base, int ctx,
260 __reset_context(base, ctx);
263 SET_TRE(base, ctx, 1);
264 SET_AFE(base, ctx, 1);
268 SET_TLBMCFG(base, ctx, 0x3);
271 SET_V2PCFG(base, ctx, 0x3);
273 SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr);
274 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr);
275 SET_TTBR1(base, ctx, 0);
278 SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr);
279 SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr);
282 SET_CTX_TLBIALL(base, ctx, 0);
285 SET_IRPTNDX(base, ctx, 0);
288 SET_CFEIE(base, ctx, 1);
291 SET_CFCFG(base, ctx, 1);
294 SET_RCISH(base, ctx, 1);
295 SET_RCOSH(base, ctx, 1);
296 SET_RCNSH(base, ctx, 1);
299 SET_BFBDFE(base, ctx, 1);
302 SET_M(base, ctx, 1);
432 __program_context(iommu->base, master->num,
465 __reset_context(iommu->base, master->num);
541 SET_CTX_TLBIALL(iommu->base, master->num, 0);
542 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);
544 par = GET_PAR(iommu->base, master->num);
547 if (GET_NOFAULT_SS(iommu->base, master->num))
552 if (GET_FAULT(iommu->base, master->num))
561 static void print_ctx_regs(void __iomem *base, int ctx)
563 unsigned int fsr = GET_FSR(base, ctx);
565 GET_FAR(base, ctx), GET_PAR(base, ctx));
579 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
581 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
583 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
656 pr_err("base = %08x\n", (unsigned int)iommu->base);
663 fsr = GET_FSR(iommu->base, i);
667 print_ctx_regs(iommu->base, i);
668 SET_FSR(iommu->base, i, 0x4000000F);
739 iommu->base = devm_ioremap_resource(iommu->dev, r);
740 if (IS_ERR(iommu->base)) {
741 ret = dev_err_probe(iommu->dev, PTR_ERR(iommu->base), "could not get iommu base\n");
759 msm_iommu_reset(iommu->base, iommu->ncb);
760 SET_M(iommu->base, 0, 1);
761 SET_PAR(iommu->base, 0, 0);
762 SET_V2PCFG(iommu->base, 0, 1);
763 SET_V2PPR(iommu->base, 0, 0);
764 par = GET_PAR(iommu->base, 0);
765 SET_V2PCFG(iommu->base, 0, 0);
766 SET_M(iommu->base, 0, 0);
800 iommu->base, iommu->irq, iommu->ncb);