Lines Matching defs:addr
35 #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
72 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
76 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
78 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
83 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
86 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
93 #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
267 #define DMA_ID_TLB_ADDR(addr) (addr)
409 #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
420 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
435 #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
523 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
654 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
731 struct intel_iommu *iommu, void *addr, int size)
734 clflush_cache_range(addr, size);
817 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
820 u16 qdep, u64 addr, unsigned mask);
822 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
826 u32 pasid, u16 qdep, u64 addr,
934 "rid=0x%llx addr=0x%llx %c%c%c%c%c pasid=0x%llx index=0x%llx",