Lines Matching defs:iommu
17 #include "iommu.h"
117 struct intel_iommu *iommu;
123 for_each_active_iommu(iommu, drhd) {
131 iommu->name, drhd->reg_base_addr);
137 raw_spin_lock_irqsave(&iommu->register_lock, flag);
139 value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);
145 value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);
150 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
218 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)
240 context = iommu_context_addr(iommu, bus, devfn, 0);
249 tbl_wlk.rt_entry = &iommu->root_entry[bus];
253 if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {
264 static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu)
268 spin_lock(&iommu->lock);
269 seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name,
270 (u64)virt_to_phys(iommu->root_entry));
279 ctx_tbl_walk(m, iommu, bus);
280 spin_unlock(&iommu->lock);
286 struct intel_iommu *iommu;
290 for_each_active_iommu(iommu, drhd) {
291 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
294 iommu->name);
297 root_tbl_walk(m, iommu);
375 * All devices in an iommu group share a single domain, hence
397 struct intel_iommu *iommu)
399 int index, shift = qi_shift(iommu);
403 if (ecap_smts(iommu->ecap))
410 desc = iommu->qi->desc + offset;
411 if (ecap_smts(iommu->ecap))
415 iommu->qi->desc_status[index]);
419 iommu->qi->desc_status[index]);
426 struct intel_iommu *iommu;
432 for_each_active_iommu(iommu, drhd) {
433 qi = iommu->qi;
434 shift = qi_shift(iommu);
436 if (!qi || !ecap_qis(iommu->ecap))
439 seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name);
444 dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,
445 dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);
446 invalidation_queue_entry_show(m, iommu);
458 struct intel_iommu *iommu)
468 ri_entry = &iommu->ir_table->base[idx];
482 struct intel_iommu *iommu)
492 pi_entry = &iommu->ir_table->base[idx];
514 struct intel_iommu *iommu;
519 for_each_active_iommu(iommu, drhd) {
520 if (!ecap_ir_support(iommu->ecap))
524 iommu->name);
526 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
527 if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {
528 irta = virt_to_phys(iommu->ir_table->base);
530 ir_tbl_remap_entry_show(m, iommu);
539 for_each_active_iommu(iommu, drhd) {
540 if (!cap_pi_support(iommu->cap))
544 iommu->name);
546 if (iommu->ir_table) {
547 irta = virt_to_phys(iommu->ir_table->base);
549 ir_tbl_posted_entry_show(m, iommu);
562 static void latency_show_one(struct seq_file *m, struct intel_iommu *iommu,
568 iommu->name, drhd->reg_base_addr);
570 ret = dmar_latency_snapshot(iommu, debug_buf, DEBUG_BUFFER_SIZE);
581 struct intel_iommu *iommu;
584 for_each_active_iommu(iommu, drhd)
585 latency_show_one(m, iommu, drhd);
601 struct intel_iommu *iommu;
619 for_each_active_iommu(iommu, drhd) {
620 dmar_latency_disable(iommu, DMAR_LATENCY_INV_IOTLB);
621 dmar_latency_disable(iommu, DMAR_LATENCY_INV_DEVTLB);
622 dmar_latency_disable(iommu, DMAR_LATENCY_INV_IEC);
623 dmar_latency_disable(iommu, DMAR_LATENCY_PRQ);
629 for_each_active_iommu(iommu, drhd)
630 dmar_latency_enable(iommu, DMAR_LATENCY_INV_IOTLB);
635 for_each_active_iommu(iommu, drhd)
636 dmar_latency_enable(iommu, DMAR_LATENCY_INV_DEVTLB);
641 for_each_active_iommu(iommu, drhd)
642 dmar_latency_enable(iommu, DMAR_LATENCY_INV_IEC);
647 for_each_active_iommu(iommu, drhd)
648 dmar_latency_enable(iommu, DMAR_LATENCY_PRQ);