Lines Matching refs:smmu
7 #include <linux/adreno-smmu-priv.h>
12 #include "arm-smmu.h"
13 #include "arm-smmu-qcom.h"
17 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
19 return container_of(smmu, struct qcom_smmu, smmu);
22 static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
28 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL);
31 reg = arm_smmu_readl(smmu, page, status);
39 qcom_smmu_tlb_sync_debug(smmu);
42 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
45 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
56 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
64 struct arm_smmu_device *smmu = smmu_domain->smmu;
66 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);
67 info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);
68 info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
69 info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
70 info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
71 info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
72 info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
79 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);
91 struct arm_smmu_device *smmu = smmu_domain->smmu;
97 arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
142 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
172 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);
178 struct arm_smmu_device *smmu,
192 count = smmu->num_context_banks;
195 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
198 static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)
200 const struct device_node *np = smmu->dev->of_node;
202 if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))
220 * All targets that use the qcom,adreno-smmu compatible string *should*
221 * be AARCH64 stage 1 but double check because the arm-smmu code assumes
224 if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&
272 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
274 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
287 if (smmu->num_mapping_groups > 128) {
288 dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");
289 smmu->num_mapping_groups = 128;
292 last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
303 arm_smmu_gr0_write(smmu, last_s2cr, reg);
304 reg = arm_smmu_gr0_read(smmu, last_s2cr);
307 qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
309 set_bit(qsmmu->bypass_cbndx, smmu->context_map);
311 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
314 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
317 for (i = 0; i < smmu->num_mapping_groups; i++) {
318 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
323 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
324 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
325 smmu->smrs[i].valid = true;
327 smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
328 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
329 smmu->s2crs[i].cbndx = 0xff;
336 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
338 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
339 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
368 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
379 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
383 arm_mmu500_reset(smmu);
393 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");
441 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
444 const struct device_node *np = smmu->dev->of_node;
451 if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))
457 return smmu;
463 qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);
467 qsmmu->smmu.impl = impl;
470 return &qsmmu->smmu;
502 * by the separate sdm845-smmu-v2 device.
514 * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
515 * special handling and can not be covered by the qcom,smmu-500 entry.
518 { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
519 { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
520 { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
521 { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data },
522 { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
523 { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
524 { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
525 { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
526 { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
527 { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
528 { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
529 { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
530 { .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
531 { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
532 { .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
533 { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
534 { .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data },
535 { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
536 { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
537 { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
538 { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
539 { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
540 { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
552 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
554 const struct device_node *np = smmu->dev->of_node;
561 return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);
567 return qcom_smmu_create(smmu, match->data);
574 WARN(of_device_is_compatible(np, "qcom,adreno-smmu"),
576 dev_name(smmu->dev));
578 return smmu;