Lines Matching refs:smmu
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
28 static u32 arm_smmu_read_ns(struct arm_smmu_device *smmu, int page,
33 return readl_relaxed(arm_smmu_page(smmu, page) + offset);
36 static void arm_smmu_write_ns(struct arm_smmu_device *smmu, int page,
41 writel_relaxed(val, arm_smmu_page(smmu, page) + offset);
52 struct arm_smmu_device smmu;
56 static int cavium_cfg_probe(struct arm_smmu_device *smmu)
59 struct cavium_smmu *cs = container_of(smmu, struct cavium_smmu, smmu);
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count);
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n");
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu,
75 struct cavium_smmu, smmu);
90 static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smmu)
94 cs = devm_krealloc(smmu->dev, smmu, sizeof(*cs), GFP_KERNEL);
98 cs->smmu.impl = &cavium_impl;
100 return &cs->smmu;
110 int arm_mmu500_reset(struct arm_smmu_device *smmu)
119 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID7);
121 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sACR);
129 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg);
135 for (i = 0; i < smmu->num_context_banks; ++i) {
136 reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
138 arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
139 reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
141 dev_warn_once(smmu->dev, "Failed to disable prefetcher [errata #841119 and #826419], check ACR.CACHE_LOCK\n");
151 static u64 mrvl_mmu500_readq(struct arm_smmu_device *smmu, int page, int off)
157 return hi_lo_readq_relaxed(arm_smmu_page(smmu, page) + off);
160 static void mrvl_mmu500_writeq(struct arm_smmu_device *smmu, int page, int off,
167 hi_lo_writeq_relaxed(val, arm_smmu_page(smmu, page) + off);
170 static int mrvl_mmu500_cfg_probe(struct arm_smmu_device *smmu)
179 smmu->features &= ~(ARM_SMMU_FEAT_FMT_AARCH64_4K |
194 struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)
196 const struct device_node *np = smmu->dev->of_node;
203 switch (smmu->model) {
205 smmu->impl = &arm_mmu500_impl;
208 return cavium_smmu_impl_init(smmu);
214 if (of_property_read_bool(np, "calxeda,smmu-secure-config-access"))
215 smmu->impl = &calxeda_impl;
217 if (of_device_is_compatible(np, "nvidia,tegra234-smmu") ||
218 of_device_is_compatible(np, "nvidia,tegra194-smmu") ||
219 of_device_is_compatible(np, "nvidia,tegra186-smmu"))
220 return nvidia_smmu_impl_init(smmu);
223 smmu = qcom_smmu_impl_init(smmu);
225 if (of_device_is_compatible(np, "marvell,ap806-smmu-500"))
226 smmu->impl = &mrvl_mmu500_impl;
228 return smmu;