Lines Matching defs:master
929 struct arm_smmu_master *master = dev_iommu_priv_get(dev);
930 int sid = master->streams[0].id;
932 if (master->stall_enabled) {
951 arm_smmu_cmdq_issue_cmd(master->smmu, &cmd);
979 struct arm_smmu_master *master;
993 list_for_each_entry(master, &smmu_domain->devices, domain_head) {
994 for (i = 0; i < master->num_streams; i++) {
995 cmd.cfgi.sid = master->streams[i].id;
1257 static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
1289 if (master) {
1290 smmu_domain = master->domain;
1291 smmu = master->smmu;
1360 !master->stall_enabled)
1385 if (master->ats_enabled)
1462 return stream->master;
1474 struct arm_smmu_master *master;
1541 master = arm_smmu_find_master(smmu, sid);
1542 if (!master) {
1547 ret = iommu_report_device_fault(master->dev, &fault_evt);
1555 arm_smmu_page_response(master->dev, &fault_evt, &resp);
1792 static int arm_smmu_atc_inv_master(struct arm_smmu_master *master)
1801 for (i = 0; i < master->num_streams; i++) {
1802 cmd.atc.sid = master->streams[i].id;
1803 arm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd);
1806 return arm_smmu_cmdq_batch_submit(master->smmu, &cmds);
1815 struct arm_smmu_master *master;
1843 list_for_each_entry(master, &smmu_domain->devices, domain_head) {
1844 if (!master->ats_enabled)
1847 for (i = 0; i < master->num_streams; i++) {
1848 cmd.atc.sid = master->streams[i].id;
2020 struct arm_smmu_master *master = dev_iommu_priv_get(dev);
2025 return master->smmu->features & ARM_SMMU_FEAT_COHERENCY;
2049 * master.
2090 struct arm_smmu_master *master,
2108 cfg->s1cdmax = master->ssid_bits;
2110 smmu_domain->stall_enabled = master->stall_enabled;
2129 * the master has been added to the devices list for this domain.
2149 struct arm_smmu_master *master,
2177 struct arm_smmu_master *master)
2237 ret = finalise_stage_fn(smmu_domain, master, &pgtbl_cfg);
2269 static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)
2272 struct arm_smmu_device *smmu = master->smmu;
2274 for (i = 0; i < master->num_streams; ++i) {
2275 u32 sid = master->streams[i].id;
2280 if (master->streams[j].id == sid)
2285 arm_smmu_write_strtab_ent(master, sid, step);
2289 static bool arm_smmu_ats_supported(struct arm_smmu_master *master)
2291 struct device *dev = master->dev;
2292 struct arm_smmu_device *smmu = master->smmu;
2304 static void arm_smmu_enable_ats(struct arm_smmu_master *master)
2308 struct arm_smmu_device *smmu = master->smmu;
2309 struct arm_smmu_domain *smmu_domain = master->domain;
2312 if (!master->ats_enabled)
2317 pdev = to_pci_dev(master->dev);
2322 dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu);
2325 static void arm_smmu_disable_ats(struct arm_smmu_master *master)
2327 struct arm_smmu_domain *smmu_domain = master->domain;
2329 if (!master->ats_enabled)
2332 pci_disable_ats(to_pci_dev(master->dev));
2338 arm_smmu_atc_inv_master(master);
2342 static int arm_smmu_enable_pasid(struct arm_smmu_master *master)
2349 if (!dev_is_pci(master->dev))
2352 pdev = to_pci_dev(master->dev);
2368 master->ssid_bits = min_t(u8, ilog2(num_pasids),
2369 master->smmu->ssid_bits);
2373 static void arm_smmu_disable_pasid(struct arm_smmu_master *master)
2377 if (!dev_is_pci(master->dev))
2380 pdev = to_pci_dev(master->dev);
2385 master->ssid_bits = 0;
2389 static void arm_smmu_detach_dev(struct arm_smmu_master *master)
2392 struct arm_smmu_domain *smmu_domain = master->domain;
2397 arm_smmu_disable_ats(master);
2400 list_del(&master->domain_head);
2403 master->domain = NULL;
2404 master->ats_enabled = false;
2405 arm_smmu_install_ste_for_dev(master);
2415 struct arm_smmu_master *master;
2420 master = dev_iommu_priv_get(dev);
2421 smmu = master->smmu;
2428 if (arm_smmu_master_sva_enabled(master)) {
2433 arm_smmu_detach_dev(master);
2439 ret = arm_smmu_domain_finalise(domain, master);
2448 master->ssid_bits != smmu_domain->s1_cfg.s1cdmax) {
2452 smmu_domain->stall_enabled != master->stall_enabled) {
2457 master->domain = smmu_domain;
2467 master->ats_enabled = arm_smmu_ats_supported(master);
2469 arm_smmu_install_ste_for_dev(master);
2472 list_add(&master->domain_head, &smmu_domain->devices);
2475 arm_smmu_enable_ats(master);
2574 struct arm_smmu_master *master)
2580 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev);
2582 master->streams = kcalloc(fwspec->num_ids, sizeof(*master->streams),
2584 if (!master->streams)
2586 master->num_streams = fwspec->num_ids;
2592 new_stream = &master->streams[i];
2594 new_stream->master = master;
2611 dev_warn(master->dev,
2627 rb_erase(&master->streams[i].node, &smmu->streams);
2628 kfree(master->streams);
2635 static void arm_smmu_remove_master(struct arm_smmu_master *master)
2638 struct arm_smmu_device *smmu = master->smmu;
2639 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev);
2641 if (!smmu || !master->streams)
2646 rb_erase(&master->streams[i].node, &smmu->streams);
2649 kfree(master->streams);
2658 struct arm_smmu_master *master;
2671 master = kzalloc(sizeof(*master), GFP_KERNEL);
2672 if (!master)
2675 master->dev = dev;
2676 master->smmu = smmu;
2677 INIT_LIST_HEAD(&master->bonds);
2678 dev_iommu_priv_set(dev, master);
2680 ret = arm_smmu_insert_master(smmu, master);
2684 device_property_read_u32(dev, "pasid-num-bits", &master->ssid_bits);
2685 master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits);
2695 arm_smmu_enable_pasid(master);
2698 master->ssid_bits = min_t(u8, master->ssid_bits,
2704 master->stall_enabled = true;
2709 kfree(master);
2716 struct arm_smmu_master *master = dev_iommu_priv_get(dev);
2718 if (WARN_ON(arm_smmu_master_sva_enabled(master)))
2719 iopf_queue_remove_device(master->smmu->evtq.iopf, dev);
2720 arm_smmu_detach_dev(master);
2721 arm_smmu_disable_pasid(master);
2722 arm_smmu_remove_master(master);
2723 kfree(master);
2782 struct arm_smmu_master *master = dev_iommu_priv_get(dev);
2784 if (!master)
2789 if (!arm_smmu_master_iopf_supported(master))
2791 if (master->iopf_enabled)
2793 master->iopf_enabled = true;
2796 if (!arm_smmu_master_sva_supported(master))
2798 if (arm_smmu_master_sva_enabled(master))
2800 return arm_smmu_master_enable_sva(master);
2809 struct arm_smmu_master *master = dev_iommu_priv_get(dev);
2811 if (!master)
2816 if (!master->iopf_enabled)
2818 if (master->sva_enabled)
2820 master->iopf_enabled = false;
2823 if (!arm_smmu_master_sva_enabled(master))
2825 return arm_smmu_master_disable_sva(master);