Lines Matching defs:enables
3300 u32 reg, enables;
3343 enables = CR0_CMDQEN;
3344 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
3369 enables |= CR0_EVTQEN;
3370 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
3386 enables |= CR0_PRIQEN;
3387 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
3396 enables |= CR0_ATSCHK;
3397 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
3412 enables &= ~(CR0_EVTQEN | CR0_PRIQEN);
3416 enables |= CR0_SMMUEN;
3422 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,