Lines Matching refs:pasid
600 u32 pasid;
605 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
621 amd_iommu_report_page_fault(iommu, devid, pasid, address, flags);
627 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
629 pasid, address, flags);
639 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%04x:%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
641 pasid, address, flags);
657 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
659 pasid, address, flags);
668 pasid = PPR_PASID(*((u64 *)__evt));
670 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
672 pasid, address, flags, tag);
714 fault.pasid = PPR_PASID(raw[0]);
1058 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid,
1065 cmd->data[0] = pasid;
1076 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1084 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
1087 cmd->data[1] |= (pasid & 0xff) << 16;
1096 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1103 cmd->data[1] = pasid;
2575 static int __flush_pasid(struct protection_domain *domain, u32 pasid,
2585 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2619 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2637 static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid,
2640 return __flush_pasid(domain, pasid, address, false);
2643 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
2651 ret = __amd_iommu_flush_page(domain, pasid, address);
2658 static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid)
2660 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2664 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
2671 ret = __amd_iommu_flush_tlb(domain, pasid);
2678 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
2685 index = (pasid >> (9 * level)) & 0x1ff;
2710 static int __set_gcr3(struct protection_domain *domain, u32 pasid,
2718 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
2724 return __amd_iommu_flush_tlb(domain, pasid);
2727 static int __clear_gcr3(struct protection_domain *domain, u32 pasid)
2734 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
2740 return __amd_iommu_flush_tlb(domain, pasid);
2743 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
2751 ret = __set_gcr3(domain, pasid, cr3);
2758 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid)
2765 ret = __clear_gcr3(domain, pasid);
2772 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
2784 build_complete_ppr(&cmd, dev_data->devid, pasid, status,