Lines Matching defs:level
100 * Free the next level. No need to look at l1 tables here since
147 * This function is used to add another level to an IO page table. Adding
148 * another level increases the size of the address space by 9 bits to a size up
202 int level, end_lvl;
217 level = domain->iop.mode - 1;
218 pte = &domain->iop.root[PM_LEVEL_INDEX(level, address)];
222 while (level > end_lvl) {
258 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
269 /* No level skipping support yet */
270 if (pte_level != level)
273 level -= 1;
277 if (pte_page && level == end_lvl)
280 pte = &pte[PM_LEVEL_INDEX(level, address)];
294 int level;
302 level = pgtable->mode - 1;
303 pte = &pgtable->root[PM_LEVEL_INDEX(level, address)];
304 *page_size = PTE_LEVEL_PAGE_SIZE(level);
306 while (level > 0) {
317 /* No level skipping support yet */
318 if (PM_PTE_LEVEL(*pte) != level)
321 level -= 1;
323 /* Walk to the next level */
325 pte = &pte[PM_LEVEL_INDEX(level, address)];
326 *page_size = PTE_LEVEL_PAGE_SIZE(level);
360 * supporting all features of AMD IOMMU page tables like level skipping