Lines Matching defs:val
2001 u64 val = qib_read_kreg64(dd, kr_intgranted);
2003 if (val)
2004 qib_write_kreg(dd, kr_intgranted, val);
2298 u64 val;
2322 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2323 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2324 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2326 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2327 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2330 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2331 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2354 u64 val, guid, ibc;
2448 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2449 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2450 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2451 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2471 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2473 qib_write_kreg_port(ppd, krp_ibcctrl_a, val);
2476 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd);
2485 val = qib_read_kreg_port(ppd, krp_errmask);
2487 val | ERR_MASK_N(IBStatusChanged));
2500 u64 val;
2542 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2544 val -= val - ppd->cpspec->ibsymsnap;
2545 val -= ppd->cpspec->ibsymdelta;
2546 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2549 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2551 val -= val - ppd->cpspec->iblnkerrsnap;
2552 val -= ppd->cpspec->iblnkerrdelta;
2553 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2556 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2557 val += ppd->cpspec->iblnkdowndelta;
2558 write_7322_creg_port(ppd, crp_iblinkdown, val);
2595 u64 extctl, ledblink = 0, val;
2611 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2612 grn = qib_7322_phys_portstate(val) ==
2614 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
3605 u64 val;
3666 val = dd->control | QLOGIC_IB_C_RESET;
3667 writeq(val, &dd->kregbase[kr_control]);
3683 val = readq(&dd->kregbase[kr_revision]);
3684 if (val == dd->revision)
4042 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
4054 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
4066 val & (val >> 16) & SendIBSLIDAssignMask);
4068 (val >> 16) & SendIBSLMCMask);
4072 ppd->link_width_enabled = val;
4074 if (val == IB_WIDTH_1X)
4075 val = 0;
4076 else if (val == IB_WIDTH_4X)
4077 val = 1;
4079 val = 3;
4092 ppd->link_speed_enabled = val;
4093 val <<= IBA7322_IBC_SPEED_LSB;
4096 if (val & (val - 1)) {
4098 val |= IBA7322_IBC_IBTA_1_2_MASK |
4103 } else if (val & IBA7322_IBC_SPEED_QDR)
4104 val |= IBA7322_IBC_IBTA_1_2_MASK;
4122 if (maskr != val) {
4125 ppd->cpspec->ibcctrl_a |= (u64) val <<
4136 if (maskr != val) {
4139 ppd->cpspec->ibcctrl_a |= (u64) val <<
4156 if (val == IB_LINKINITCMD_POLL)
4174 val = (ppd->ibmaxlen >> 2) + 1;
4176 ppd->cpspec->ibcctrl_a |= (u64)val <<
4184 switch (val & 0xffff0000) {
4219 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
4222 switch (val & 0xffff) {
4251 val & 0xffff);
4258 if (ppd->vls_operational != val) {
4259 ppd->vls_operational = val;
4265 qib_write_kreg_port(ppd, krp_highprio_limit, val);
4269 if (val > 3) {
4278 /* val is the port number of the switch we are connected to. */
4290 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
4300 u64 val, ctrlb;
4306 val = 0; /* disable heart beat, so link will come up */
4313 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
4324 ppd->cpspec->ibcctrl_b = ctrlb | val;
4338 u32 val = qib_read_kreg_port(ppd, regno);
4340 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
4342 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
4353 u64 val;
4355 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
4359 qib_write_kreg_port(ppd, regno, val);
4462 u64 mask, val;
4527 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4528 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4532 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4533 dd->rcd[ctxt]->head = val;
4536 val |= dd->rhdrhead_intr_off;
4537 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4541 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4542 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
5163 u64 val;
5169 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
5176 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
5178 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
5723 u64 val;
5737 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5738 dd->piobcnt2k = val & ~0U;
5739 dd->piobcnt4k = val >> 32;
5740 val = qib_read_kreg64(dd, kr_sendpiosize);
5741 dd->piosize2k = val & ~0U;
5742 dd->piosize4k = val >> 32;
5877 * New shadow val is bits we don't want to touch,
6029 unsigned long val;
6060 val = simple_strtoul(str, &nxt, 0);
6066 if (val >= txdds_size)
6085 ppd->cpspec->no_eep = val;
6116 unsigned long index, val;
6123 val = simple_strtoul(str, &n, 0);
6124 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
6146 u64 val;
6152 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
6153 if (val != dd->pioavailregs_phys) {
6157 (unsigned long long) val);
6209 u64 val;
6225 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
6226 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
6227 val |= (u64)(ppd->vls_supported - 1) <<
6229 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
6263 u64 val;
6285 val = 0;
6299 val |= ctxt << (5 * (i % 6));
6302 qib_write_kreg_port(ppd, regno, val);
6303 val = 0;
6307 qib_write_kreg_port(ppd, regno, val);
6326 val = TIDFLOW_ERRBITS; /* these are W1C */
6331 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
7136 static void writescratch(struct qib_devdata *dd, u32 val)
7138 qib_write_kreg(dd, kr_scratch, val);
8227 u64 val = SJA_EN;
8229 qib_write_kreg(dd, kr_r_access, val);
8239 u64 val;
8243 val = qib_read_kreg32(dd, kr_r_access);
8244 if (val & R_RDY)
8245 return (val >> R_TDO_LSB) & 1;
8253 u64 valbase, val;
8262 val = valbase;
8270 val |= ((tdi & 1) << R_TDI_LSB);
8272 qib_write_kreg(dd, kr_r_access, val);
8279 val = SJA_EN | (bisten << BISTEN_LSB);
8280 qib_write_kreg(dd, kr_r_access, val);
8292 u64 val;
8295 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
8298 qib_write_kreg(dd, kr_r_access, val);