Lines Matching defs:mask
555 u64 gpio_mask; /* shadow the gpio mask register */
702 u64 mask;
1178 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1180 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1199 { .mask = 0, .sz = 0 }
1202 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1204 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1221 { .mask = 0, .sz = 0 }
1231 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted",
1268 { .mask = 0, .sz = 0 }
1275 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1278 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1283 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1291 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1297 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \
1307 { .mask = 0, .sz = 0 }
1352 while (errs && msp && msp->mask) {
1353 multi = (msp->mask & (msp->mask - 1));
1354 while (errs & msp->mask) {
1355 these = (errs & msp->mask);
1373 /* More than one bit this mask */
1376 while (lmask & msp->mask) {
1633 u64 mask;
1665 * The ones we mask off are handled specially below
1666 * or above. Also mask SDMADISABLED by default as it
1669 mask = QIB_E_HARDWARE;
1672 err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask,
2021 * the *mask value).
2053 /* We need to purge per-port errs and reset mask, too */
2187 * we can enable hardware errors in the mask (potentially enabling
2682 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask;
2765 const cpumask_t *mask)
2769 int cpu = cpumask_first(mask);
2818 free_cpumask_var(dd->cspec->msix_entries[i].mask);
2859 u32 mask = QSFP_GPIO_MOD_PRS_N |
2865 dd->cspec->gpio_mask &= ~mask;
2938 * the bits in the mask, since there is some kind of
2958 u32 mask;
2962 mask = QSFP_GPIO_MOD_PRS_N;
2964 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2965 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2969 gpiostatus &= ~mask;
2972 if (!(pins & mask)) {
2981 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
2982 u32 gpio_irq = mask & gpiostatus;
3359 u64 mask;
3374 /* clear the reset error, init error/hwerror mask */
3403 mask = ~0ULL;
3488 mask &= ~(1ULL << lsb);
3495 &dd->cspec->msix_entries[msixnum].mask,
3499 dd->cspec->msix_entries[msixnum].mask);
3506 dd->cspec->msix_entries[msixnum].mask);
3510 dd->cspec->msix_entries[msixnum].mask);
3517 dd->cspec->main_int_mask = mask;
3943 u64 maskr; /* right-justified mask */
4045 u64 maskr; /* right-justified mask */
4062 * set any bits not covered by the mask, or we get
4454 * generic. <op> is a bit-mask because we often want to
4462 u64 mask, val;
4480 mask = (1ULL << dd->ctxtcnt) - 1;
4483 mask = (1ULL << ctxt);
4488 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4502 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4504 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4506 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4508 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4510 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4700 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
5667 * set output and direction bits selected by mask.
5672 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5677 if (mask) {
5679 dir &= mask;
5680 out &= mask;
5682 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5684 new_out = (dd->cspec->gpio_out & ~mask) | out;
5707 u32 mask;
5709 mask = 1 << QIB_EEPROM_WEN_NUM;
5711 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5815 u64 *data, u64 mask, int only_32)
5855 if (!ppd || (mask & all_bits) != all_bits) {
5857 * At least some mask bits are zero, so we need
5867 *data = (local_data & ~mask) | (*data & mask);
5869 if (mask) {
5871 * At least some mask bits are one, so we need
5881 sval = ppd->p_sendctrl & ~mask;
5882 sval |= *data & SENDCTRL_SHADOWED & mask;
5885 sval = *data & SENDCTRL_SHADOWED & mask;
5886 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
7706 u32 data, u32 mask)
7728 /* If mask is not all 1s, we need to read, but different SerDes
7732 wr_data = data & mask & sz_mask;
7733 if ((~mask & sz_mask) != 0) {
7750 wr_data |= (rd_data & ~mask & sz_mask);
7753 /* If mask is not zero, we need to write. */
7754 if (mask & sz_mask) {
7778 unsigned mask)
7785 data, mask);