Lines Matching defs:cspec
880 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
882 return readq(&dd->cspec->cregbase[regno]);
889 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
891 return readl(&dd->cspec->cregbase[regno]);
1499 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1644 errs &= dd->cspec->errormask;
1645 msg = dd->cspec->emsgbuf;
1650 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
1672 err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask,
1719 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1782 if (!ppd->dd->cspec->r1)
1803 if (!ppd->dd->cspec->r1 &&
1818 ppd->dd->cspec->r1 ?
1996 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
1999 if (dd->cspec->num_msix_entries) {
2052 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2096 hwerrs &= dd->cspec->hwerrmask;
2111 dd->cspec->stay_in_freeze) {
2131 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2132 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2203 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2209 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2226 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2228 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2229 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2479 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2482 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2510 if (ppd->dd->cspec->r1)
2620 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2621 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2635 dd->cspec->extctrl = extctl;
2636 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2637 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2661 dd->cspec->dca_ctrl = 0;
2663 dd->cspec->dca_ctrl);
2673 struct qib_chip_specific *cspec = dd->cspec;
2677 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) {
2680 cspec->rhdr_cpu[rcd->ctxt] = cpu;
2682 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask;
2683 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |=
2687 (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2689 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2690 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable);
2691 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2698 struct qib_chip_specific *cspec = dd->cspec;
2703 if (cspec->sdma_cpu[pidx] != cpu) {
2704 cspec->sdma_cpu[pidx] = cpu;
2705 cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ?
2708 cspec->dca_rcvhdr_ctrl[4] |=
2715 (long long) cspec->dca_rcvhdr_ctrl[4]);
2717 cspec->dca_rcvhdr_ctrl[4]);
2718 cspec->dca_ctrl |= ppd->hw_pidx ?
2721 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2727 struct qib_chip_specific *cspec = dd->cspec;
2730 for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++)
2731 cspec->rhdr_cpu[i] = -1;
2732 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2733 cspec->sdma_cpu[i] = -1;
2734 cspec->dca_rcvhdr_ctrl[0] =
2739 cspec->dca_rcvhdr_ctrl[1] =
2744 cspec->dca_rcvhdr_ctrl[2] =
2749 cspec->dca_rcvhdr_ctrl[3] =
2754 cspec->dca_rcvhdr_ctrl[4] =
2757 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2759 cspec->dca_rcvhdr_ctrl[i]);
2760 for (i = 0; i < cspec->num_msix_entries; i++)
2808 dd->cspec->main_int_mask = ~0ULL;
2810 for (i = 0; i < dd->cspec->num_msix_entries; i++) {
2812 if (dd->cspec->msix_entries[i].arg) {
2818 free_cpumask_var(dd->cspec->msix_entries[i].mask);
2820 dd->cspec->msix_entries[i].arg);
2825 if (!dd->cspec->num_msix_entries)
2828 dd->cspec->num_msix_entries = 0;
2846 dd->cspec->dca_ctrl = 0;
2847 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl);
2852 kfree(dd->cspec->cntrs);
2853 bitmap_free(dd->cspec->sendchkenable);
2854 bitmap_free(dd->cspec->sendgrhchk);
2855 bitmap_free(dd->cspec->sendibchk);
2856 kfree(dd->cspec->msix_entries);
2864 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2865 dd->cspec->gpio_mask &= ~mask;
2866 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2867 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2924 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2965 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2987 dd->cspec->gpio_mask &= ~gpio_irq;
2988 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
3019 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
3032 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
3075 istat &= dd->cspec->main_int_mask;
3306 if (!dd->cspec->msix_entries[msixnum].dca)
3312 dd->cspec->msix_entries[msixnum].notifier = NULL;
3317 struct qib_msix_entry *m = &dd->cspec->msix_entries[msixnum];
3385 if (!dd->cspec->num_msix_entries) {
3397 dd->cspec->main_int_mask = ~0ULL;
3418 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3478 dd->cspec->msix_entries[msixnum].arg = arg;
3480 dd->cspec->msix_entries[msixnum].dca = dca;
3481 dd->cspec->msix_entries[msixnum].rcv =
3495 &dd->cspec->msix_entries[msixnum].mask,
3499 dd->cspec->msix_entries[msixnum].mask);
3506 dd->cspec->msix_entries[msixnum].mask);
3510 dd->cspec->msix_entries[msixnum].mask);
3517 dd->cspec->main_int_mask = mask;
3617 msix_entries = dd->cspec->num_msix_entries;
3626 msix_vecsave = kmalloc_array(2 * dd->cspec->num_msix_entries,
3719 dd->cspec->num_msix_entries = msix_entries;
3854 if (rcd->dd->cspec->r1)
3880 dd->cspec->numctxts = nchipctxts;
3913 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3928 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3931 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3933 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3935 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt,
4279 if (ppd->dd->cspec->r1) {
4465 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4567 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4979 dd->cspec->ncntrs = i;
4982 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
4984 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
4985 dd->cspec->cntrs = kmalloc_array(dd->cspec->ncntrs, sizeof(u64),
4990 dd->cspec->nportcntrs = i - 1;
4991 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
4994 kmalloc_array(dd->cspec->nportcntrs, sizeof(u64),
5005 ret = dd->cspec->cntrnamelen;
5011 u64 *cntr = dd->cspec->cntrs;
5014 ret = dd->cspec->ncntrs * sizeof(u64);
5021 for (i = 0; i < dd->cspec->ncntrs; i++)
5040 ret = dd->cspec->portcntrnamelen;
5050 ret = dd->cspec->nportcntrs * sizeof(u64);
5057 for (i = 0; i < dd->cspec->nportcntrs; i++) {
5126 ppd->dd->cspec->r1 ?
5140 if (!dd->cspec->num_msix_entries)
5171 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
5183 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
5629 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5681 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5682 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5683 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5684 new_out = (dd->cspec->gpio_out & ~mask) | out;
5686 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5688 dd->cspec->gpio_out = new_out;
5689 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5770 * The chip base addresses in cspec and cpspec have to be set
5780 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5956 if (!ret && !ppd->dd->cspec->r1) {
6004 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
6005 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
6006 dd->cspec->gpio_mask |= mod_prs_bit;
6007 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
6008 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
6009 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
6248 if (ppd->dd->cspec->r1)
6279 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
6281 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
6317 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
6357 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
6359 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
6364 spin_lock_init(&dd->cspec->rcvmod_lock);
6365 spin_lock_init(&dd->cspec->gpio_lock);
6380 dd->cspec->r1 = dd->minrev == 1;
6388 dd->cspec->sendchkenable = bitmap_zalloc(sbufcnt, GFP_KERNEL);
6389 dd->cspec->sendgrhchk = bitmap_zalloc(sbufcnt, GFP_KERNEL);
6390 dd->cspec->sendibchk = bitmap_zalloc(sbufcnt, GFP_KERNEL);
6391 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6392 !dd->cspec->sendibchk) {
6424 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6426 dd->cspec->hwerrmask = ~0ULL;
6429 dd->cspec->hwerrmask &=
6447 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6451 dd->cspec->int_enable_mask &= ~(
6462 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6466 dd->cspec->int_enable_mask &= ~(
6527 if (ppd->dd->cspec->r1)
6636 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6639 dd->cspec->sdmabufcnt = 0;
6642 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6643 dd->cspec->sdmabufcnt;
6644 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6645 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6646 dd->last_pio = dd->cspec->lastbuf_for_pio;
6658 dd->cspec->updthresh_dflt = updthresh;
6659 dd->cspec->updthresh = updthresh;
6690 last = dd->cspec->lastbuf_for_pio;
6857 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6859 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6862 dd->cspec->sdmabufcnt);
6987 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
7048 clear_bit(i, dd->cspec->sendchkenable);
7060 set_bit(i, dd->cspec->sendchkenable);
7066 set_bit(i, dd->cspec->sendibchk);
7067 clear_bit(i, dd->cspec->sendgrhchk);
7072 dd->cspec->updthresh != dd->cspec->updthresh_dflt
7076 < dd->cspec->updthresh_dflt)
7081 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
7083 dd->sendctrl |= (dd->cspec->updthresh &
7094 clear_bit(i, dd->cspec->sendibchk);
7095 set_bit(i, dd->cspec->sendgrhchk);
7099 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
7100 dd->cspec->updthresh = (rcd->piocnt /
7103 dd->sendctrl |= (dd->cspec->updthresh &
7118 dd->cspec->sendchkenable[i]);
7122 dd->cspec->sendgrhchk[i]);
7124 dd->cspec->sendibchk[i]);
7261 dd->cspec->msix_entries = kcalloc(tabsize,
7264 if (!dd->cspec->msix_entries)
7271 dd->cspec->num_msix_entries = tabsize;
7812 if (ppd->dd->cspec->r1)
7887 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7897 ppd->dd->cspec->r1 ?
7907 if (!ppd->dd->cspec->r1) {
7967 if (!ppd->dd->cspec->r1) {
8067 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
8088 ppd->dd->cspec->r1 ?
8203 if (!ppd->dd->cspec->r1)
8404 if (!ppd->dd->cspec->r1)
8407 dd->cspec->recovery_ports_initted++;
8410 if (!both && dd->cspec->recovery_ports_initted == 1) {
8438 if (dd->cspec->recovery_ports_initted != 1)
8451 ppd->dd->cspec->stay_in_freeze = 1;