Lines Matching defs:bits
274 /* ibcctrl bits */
410 /* kr_control bits */
413 /* kr_intstatus, kr_intclear, kr_intmask bits */
432 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
447 /* kr_extstatus bits */
453 /* kr_xgxsconfig bits */
473 #define QLOGIC_IB_RT_ADDR_MASK 0x1FFFFFFFULL /* 29 bits valid */
723 * force new interrupt if any hwerr, error or interrupt bits are
749 u32 bits, ctrl;
758 "Read of hardware error status failed (all bits set); ignoring\n");
793 * hardware error bits are set), and continue. They can
826 bits = (u32) ((hwerrs >>
830 "[PCIe Mem Parity Errs %x] ", bits);
965 * It's possible that sendbuffererror could have bits set; might
1120 * cause a hardware error, and cleared those errors bits as they occur,
1270 * serdesstatus at least for simulation, or some of the bits in
1287 * Leave L1PWR bits set (permanently)
1330 /* clear current and de-emphasis bits */
1526 "error interrupt (%Lx), but no error bits set!\n",
1542 /* want to clear the bits we see asserted. */
1546 * Count appropriately, clear bits out of our copy,
1559 * Some unexpected bits remain. If they could have
1621 * Clear the interrupt bits we found set, relatively early, so we
1689 * enable interrupts on those bits so the interrupt routine
1935 * Used from qib_close(). On this chip, TIDs are only 32 bits,
1937 * is declared as u64 * for the pointer math, even though we write 32 bits
3029 * set output and direction bits selected by mask.
3040 /* some bits being written, lock access to GPIO */
3202 * GPIO bits for TWSI data and clock,