Lines Matching defs:ctrl_seg
295 err = umr_check_mkey_mask(dev, be64_to_cpu(wqe->ctrl_seg.mkey_mask));
366 wqe.ctrl_seg.mkey_mask |= get_umr_update_pd_mask();
367 wqe.ctrl_seg.mkey_mask |= get_umr_disable_mr_mask();
368 wqe.ctrl_seg.flags |= MLX5_UMR_INLINE;
404 wqe.ctrl_seg.mkey_mask = get_umr_update_access_mask(dev);
405 wqe.ctrl_seg.mkey_mask |= get_umr_update_pd_mask();
406 wqe.ctrl_seg.flags = MLX5_UMR_CHECK_FREE;
407 wqe.ctrl_seg.flags |= MLX5_UMR_INLINE;
527 mlx5r_umr_set_update_xlt_ctrl_seg(struct mlx5_wqe_umr_ctrl_seg *ctrl_seg,
532 ctrl_seg->flags = MLX5_UMR_CHECK_FREE;
535 ctrl_seg->flags = MLX5_UMR_CHECK_NOT_FREE;
536 ctrl_seg->xlt_octowords =
563 static void mlx5r_umr_update_offset(struct mlx5_wqe_umr_ctrl_seg *ctrl_seg,
568 ctrl_seg->xlt_offset = cpu_to_be16(octo_offset & 0xffff);
569 ctrl_seg->xlt_offset_47_16 = cpu_to_be32(octo_offset >> 16);
570 ctrl_seg->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
581 wqe->ctrl_seg.mkey_mask |= get_umr_enable_mr_mask();
588 wqe->ctrl_seg.mkey_mask |= get_umr_update_access_mask(dev);
589 wqe->ctrl_seg.mkey_mask |= get_umr_update_pd_mask();
596 wqe->ctrl_seg.mkey_mask |= get_umr_update_translation_mask();
601 wqe->ctrl_seg.xlt_octowords =
636 mlx5r_umr_set_update_xlt_ctrl_seg(&wqe.ctrl_seg, flags, &sg);
654 mlx5r_umr_update_offset(&wqe.ctrl_seg, offset);
738 mlx5r_umr_set_update_xlt_ctrl_seg(&wqe.ctrl_seg, flags, &sg);
756 mlx5r_umr_update_offset(&wqe.ctrl_seg, idx * desc_size);