Lines Matching defs:props
473 struct ib_port_attr *props)
497 /* Possible bad flows are checked before filling out props so in case
512 props->active_width = IB_WIDTH_4X;
513 props->active_speed = IB_SPEED_QDR;
515 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
516 &props->active_width, ext);
521 props->port_cap_flags |= IB_PORT_CM_SUP;
522 props->ip_gids = true;
523 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
526 props->qkey_viol_cntr = qkey_viol_cntr;
528 props->max_mtu = IB_MTU_4096;
529 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
530 props->pkey_tbl_len = 1;
531 props->state = IB_PORT_DOWN;
532 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
554 props->state = IB_PORT_ACTIVE;
555 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
562 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
672 struct ib_device_attr *props)
686 props->atomic_cap = IB_ATOMIC_HCA;
688 props->atomic_cap = IB_ATOMIC_NONE;
693 struct ib_device_attr *props)
697 get_atomic_caps(dev, atomic_size_qp, props);
818 struct ib_device_attr *props,
843 memset(props, 0, sizeof(*props));
845 &props->sys_image_guid);
849 props->max_pkeys = dev->pkey_table_len;
851 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
855 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
858 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
864 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
866 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
868 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
870 props->device_cap_flags |= IB_DEVICE_XRC;
872 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
874 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
876 props->kernel_cap_flags |= IBK_SG_GAPS_REG;
880 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
882 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER;
884 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
887 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
891 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK;
896 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
897 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
901 props->raw_packet_caps |=
937 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
938 props->kernel_cap_flags |= IBK_UD_TSO;
944 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
948 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
954 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
955 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
959 props->max_dm_size =
964 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
967 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
969 props->vendor_part_id = mdev->pdev->device;
970 props->hw_ver = mdev->pdev->revision;
972 props->max_mr_size = ~0ull;
973 props->page_size_cap = ~(min_page_size - 1);
974 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
975 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
982 props->max_send_sge = max_sq_sg;
983 props->max_recv_sge = max_rq_sg;
984 props->max_sge_rd = MLX5_MAX_SGE_RD;
985 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
986 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
987 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
988 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
989 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
990 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
991 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
992 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
993 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
994 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
995 props->max_srq_sge = max_rq_sg - 1;
996 props->max_fast_reg_page_list_len =
998 props->max_pi_fast_reg_page_list_len =
999 props->max_fast_reg_page_list_len / 2;
1000 props->max_sgl_rd =
1002 get_atomic_caps_qp(dev, props);
1003 props->masked_atomic_cap = IB_ATOMIC_NONE;
1004 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1005 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
1006 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1007 props->max_mcast_grp;
1008 props->max_ah = INT_MAX;
1009 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1010 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
1014 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING;
1015 props->odp_caps = dev->odp_caps;
1020 props->odp_caps.per_transport_caps.rc_odp_caps &=
1023 props->odp_caps.per_transport_caps.uc_odp_caps &=
1026 props->odp_caps.per_transport_caps.ud_odp_caps &=
1029 props->odp_caps.per_transport_caps.xrc_odp_caps &=
1036 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION;
1040 props->rss_caps.max_rwq_indirection_tables =
1042 props->rss_caps.max_rwq_indirection_table_size =
1044 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1045 props->max_wq_type_rq =
1050 props->tm_caps.max_num_tags =
1052 props->tm_caps.max_ops =
1054 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1059 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1060 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1064 props->cq_caps.max_cq_moderation_count =
1066 props->cq_caps.max_cq_moderation_period =
1304 struct ib_port_attr *props)
1321 /* props being zeroed by the caller, avoid zeroing it here */
1327 props->lid = rep->lid;
1328 props->lmc = rep->lmc;
1329 props->sm_lid = rep->sm_lid;
1330 props->sm_sl = rep->sm_sl;
1331 props->state = rep->vport_state;
1332 props->phys_state = rep->port_physical_state;
1333 props->port_cap_flags = rep->cap_mask1;
1334 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1335 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1336 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1337 props->bad_pkey_cntr = rep->pkey_violation_counter;
1338 props->qkey_viol_cntr = rep->qkey_violation_counter;
1339 props->subnet_timeout = rep->subnet_timeout;
1340 props->init_type_reply = rep->init_type_reply;
1342 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1343 props->port_cap_flags2 = rep->cap_mask2;
1346 &props->active_speed, port);
1350 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1354 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1358 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1365 &props->max_vl_num);
1372 struct ib_port_attr *props)
1379 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1383 ret = mlx5_query_hca_port(ibdev, port, props);
1387 ret = mlx5_query_port_roce(ibdev, port, props);
1394 if (!ret && props) {
1411 props->gid_tbl_len -= count;
1417 struct ib_port_attr *props)
1419 return mlx5_query_port_roce(ibdev, port, props);
1494 struct ib_device_modify *props)
1511 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1517 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1557 struct ib_port_modify *props)
1575 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1576 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1586 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1587 ~props->clr_port_cap_mask;