Lines Matching defs:attr_mask
179 u32 var, u32 *attr_mask)
183 *attr_mask |= MLX5_IB_RP_CLAMP_TGT_RATE_ATTR;
188 *attr_mask |= MLX5_IB_RP_CLAMP_TGT_RATE_ATI_ATTR;
193 *attr_mask |= MLX5_IB_RP_TIME_RESET_ATTR;
198 *attr_mask |= MLX5_IB_RP_BYTE_RESET_ATTR;
203 *attr_mask |= MLX5_IB_RP_THRESHOLD_ATTR;
208 *attr_mask |= MLX5_IB_RP_AI_RATE_ATTR;
213 *attr_mask |= MLX5_IB_RP_MAX_RATE_ATTR;
218 *attr_mask |= MLX5_IB_RP_HAI_RATE_ATTR;
223 *attr_mask |= MLX5_IB_RP_MIN_DEC_FAC_ATTR;
228 *attr_mask |= MLX5_IB_RP_MIN_RATE_ATTR;
233 *attr_mask |= MLX5_IB_RP_RATE_TO_SET_ON_FIRST_CNP_ATTR;
238 *attr_mask |= MLX5_IB_RP_DCE_TCP_G_ATTR;
243 *attr_mask |= MLX5_IB_RP_DCE_TCP_RTT_ATTR;
248 *attr_mask |= MLX5_IB_RP_RATE_REDUCE_MONITOR_PERIOD_ATTR;
253 *attr_mask |= MLX5_IB_RP_INITIAL_ALPHA_VALUE_ATTR;
258 *attr_mask |= MLX5_IB_RP_GD_ATTR;
263 *attr_mask |= MLX5_IB_NP_MIN_TIME_BETWEEN_CNPS_ATTR;
268 *attr_mask |= MLX5_IB_NP_CNP_DSCP_ATTR;
272 *attr_mask |= MLX5_IB_NP_CNP_PRIO_MODE_ATTR;
276 *attr_mask |= MLX5_IB_NP_CNP_PRIO_MODE_ATTR;
281 *attr_mask |= MLX5_IB_GENERAL_RTT_RESP_DSCP_ATTR;
285 *attr_mask |= MLX5_IB_GENERAL_RTT_RESP_DSCP_ATTR;
337 u32 attr_mask = 0;
358 mlx5_ib_set_cc_param_mask_val(field, offset, var, &attr_mask);
362 attr_mask);