Lines Matching defs:dev
54 * @dev: pointer to the device structure
57 static void icrdma_ena_irq(struct irdma_sc_dev *dev, u32 idx)
62 if (dev->ceq_itr && dev->aeq->msix_idx != idx)
63 interval = dev->ceq_itr >> 1; /* 2 usec units */
69 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1)
70 writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
72 writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1));
77 * @dev: pointer to the device structure
80 static void icrdma_disable_irq(struct irdma_sc_dev *dev, u32 idx)
82 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1)
83 writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
85 writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1));
90 * @dev: pointer to the device structure
95 static void icrdma_cfg_ceq(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx,
104 writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id);
163 void icrdma_init_hw(struct irdma_sc_dev *dev)
169 hw_addr = dev->hw->hw_addr;
174 dev->hw_regs[i] = (u32 __iomem *)(hw_addr + icrdma_regs[i]);
176 dev->hw_attrs.max_hw_vf_fpm_id = IRDMA_MAX_VF_FPM_ID;
177 dev->hw_attrs.first_hw_vf_fpm_id = IRDMA_FIRST_VF_FPM_ID;
180 dev->hw_shifts[i] = icrdma_shifts[i];
183 dev->hw_masks[i] = icrdma_masks[i];
185 dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC];
186 dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM];
187 dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC];
188 dev->cqp_db = dev->hw_regs[IRDMA_CQPDB];
189 dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK];
190 dev->irq_ops = &icrdma_irq_ops;
191 dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M | SZ_1G;
192 dev->hw_stats_map = icrdma_hw_stat_map;
193 dev->hw_attrs.max_hw_ird = ICRDMA_MAX_IRD_SIZE;
194 dev->hw_attrs.max_hw_ord = ICRDMA_MAX_ORD_SIZE;
195 dev->hw_attrs.max_stat_inst = ICRDMA_MAX_STATS_COUNT;
196 dev->hw_attrs.max_stat_idx = IRDMA_HW_STAT_INDEX_MAX_GEN_2;
198 dev->hw_attrs.uk_attrs.min_hw_wq_size = ICRDMA_MIN_WQ_SIZE;
199 dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR;
200 dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_RTS_AE |