Lines Matching defs:read_csr
1301 * read_csr - read CSR at the indicated offset
1308 u64 read_csr(const struct hfi1_devdata *dd, u32 offset)
1356 ret = read_csr(dd, csr);
5228 mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64)));
5679 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
5680 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
6343 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
6371 (void)read_csr(dd, DCC_CFG_RESET);
6398 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
6413 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
6486 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
6487 reg = read_csr(dd, DCC_CFG_RESET);
6490 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
6719 rcvctrl = read_csr(dd, RCV_CTRL);
6790 reg = read_csr(dd, CCE_STATUS);
7504 reg = read_csr(dd, SEND_CM_CTRL);
7567 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
7741 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
7846 read_csr(dd, DC_DC8051_ERR_EN) &
7936 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
7955 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
8006 info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
8007 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
8008 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
8304 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
8335 /* This read_csr is really bad in the hot path */
8336 status = read_csr(dd,
8366 (void)read_csr(dd, addr);
8543 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
8552 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8561 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8578 *data = read_csr(dd, addr);
8658 *data = read_csr(dd, addr);
8770 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0);
8794 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
8814 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
9271 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
9488 mask = read_csr(dd, dd->hfi1_id ?
9506 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
9532 qsfp_mask = read_csr(dd,
10163 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
10176 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
10348 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);
10379 (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET);
10651 reg = read_csr(ppd->dd, SEND_CM_CREDIT_VL + (8 * i));
11177 u64 reg = read_csr(dd, csr);
11206 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11223 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
11231 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
11305 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11316 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11333 reg = read_csr(dd, addr);
11350 reg = read_csr(dd, addr);
11365 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
13158 reg = read_csr(dd, ASIC_STS_THERM);
13190 reg = read_csr(dd, CCE_INT_MASK + (8 * idx));
13283 reg = read_csr(dd, CCE_INT_MAP + (8 * m));
13606 reg = read_csr(dd, CCE_STATUS);
13616 reg = read_csr(dd, CCE_STATUS);
13834 reg = read_csr(dd, RCV_STATUS);
13863 read_csr(dd, RCV_CTRL);
13870 reg = read_csr(dd, RCV_STATUS);
14060 (void)read_csr(dd, CCE_DC_CTRL);
14164 u64 reg = read_csr(dd, RCV_QP_MAP_TABLE + (idx / 8) * 8);
14272 return read_csr(dd, RCV_RSM_CFG + (8 * rule_index)) != 0;
14543 reg = read_csr(dd, regoff);
14560 reg = read_csr(dd, regoff);
14678 val = read_csr(dd, RCV_BYPASS);
14963 mask = read_csr(dd, CCE_INT_MASK);
14965 reg = read_csr(dd, CCE_INT_MASK);
14971 reg = read_csr(dd, CCE_INT_STATUS);
14977 reg = read_csr(dd, CCE_INT_STATUS);
15094 reg = read_csr(dd, CCE_REVISION2);