Lines Matching defs:rcd
5221 /* return true is kernel urg disabled for rcd */
5222 bool is_urg_masked(struct hfi1_ctxtdata *rcd)
5225 u32 is = IS_RCVURGENT_START + rcd->ctxt;
5228 mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64)));
6818 struct hfi1_ctxtdata *rcd;
6825 rcd = hfi1_rcd_get_by_index(dd, i);
6826 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, rcd);
6827 hfi1_rcd_put(rcd);
6841 struct hfi1_ctxtdata *rcd;
6845 rcd = hfi1_rcd_get_by_index(dd, i);
6848 if (!rcd ||
6849 (i >= dd->first_dyn_alloc_ctxt && !rcd->is_vnic)) {
6850 hfi1_rcd_put(rcd);
6855 rcvmask |= hfi1_rcvhdrtail_kvaddr(rcd) ?
6857 hfi1_rcvctrl(dd, rcvmask, rcd);
6858 hfi1_rcd_put(rcd);
8170 struct hfi1_ctxtdata *rcd;
8174 rcd = hfi1_rcd_get_by_index(dd, source);
8175 if (rcd) {
8176 handle_user_interrupt(rcd);
8177 hfi1_rcd_put(rcd);
8180 /* received an interrupt, but no rcd */
8201 struct hfi1_ctxtdata *rcd;
8205 rcd = hfi1_rcd_get_by_index(dd, source);
8206 if (rcd) {
8207 handle_user_interrupt(rcd);
8208 hfi1_rcd_put(rcd);
8211 /* received an interrupt, but no rcd */
8359 static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd)
8361 struct hfi1_devdata *dd = rcd->dd;
8362 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg);
8364 write_csr(dd, addr, rcd->imask);
8370 void force_recv_intr(struct hfi1_ctxtdata *rcd)
8372 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8385 static inline int check_packet_present(struct hfi1_ctxtdata *rcd)
8389 if (hfi1_packet_present(rcd))
8393 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8394 return hfi1_rcd_head(rcd) != tail;
8402 static void receive_interrupt_common(struct hfi1_ctxtdata *rcd)
8404 struct hfi1_devdata *dd = rcd->dd;
8406 trace_hfi1_receive_interrupt(dd, rcd);
8408 aspm_ctx_disable(rcd);
8416 * @rcd: valid receive context
8418 static void __hfi1_rcd_eoi_intr(struct hfi1_ctxtdata *rcd)
8420 if (!rcd->rcvhdrq)
8422 clear_recv_intr(rcd);
8423 if (check_packet_present(rcd))
8424 force_recv_intr(rcd);
8430 * @rcd: Ptr to hfi1_ctxtdata of receive context
8439 static void hfi1_rcd_eoi_intr(struct hfi1_ctxtdata *rcd)
8444 __hfi1_rcd_eoi_intr(rcd);
8457 struct hfi1_ctxtdata *rcd = rxq->rcd;
8460 work_done = rcd->do_interrupt(rcd, budget);
8464 hfi1_rcd_eoi_intr(rcd);
8473 struct hfi1_ctxtdata *rcd = data;
8475 receive_interrupt_common(rcd);
8477 if (likely(rcd->napi)) {
8478 if (likely(napi_schedule_prep(rcd->napi)))
8479 __napi_schedule_irqoff(rcd->napi);
8481 __hfi1_rcd_eoi_intr(rcd);
8484 rcd->ctxt);
8485 __hfi1_rcd_eoi_intr(rcd);
8501 struct hfi1_ctxtdata *rcd = data;
8504 receive_interrupt_common(rcd);
8507 disposition = rcd->do_interrupt(rcd, 0);
8517 __hfi1_rcd_eoi_intr(rcd);
8527 struct hfi1_ctxtdata *rcd = data;
8530 (void)rcd->do_interrupt(rcd, 1);
8532 hfi1_rcd_eoi_intr(rcd);
9971 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd)
9973 struct hfi1_devdata *dd = rcd->dd;
9977 for (i = rcd->eager_base; i < rcd->eager_base +
9978 rcd->egrbufs.alloced; i++)
9981 for (i = rcd->expected_base;
9982 i < rcd->expected_base + rcd->expected_count; i++)
10098 * dd->rcd[0].rcvhdrqentsize is in DW.
10099 * We use rcd[0] as all context will have the same value. Also,
10103 return (get_hdrqentsize(dd->rcd[0]) - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
10148 get_hdrqentsize(dd->rcd[0])));
10157 dd->rcd[0]->rcvhdrqentsize));
11802 static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
11804 struct hfi1_devdata *dd = rcd->dd;
11805 u32 timeout = rcd->rcvavail_timeout;
11834 rcd->rcvavail_timeout = timeout;
11839 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
11844 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
11847 struct hfi1_devdata *dd = rcd->dd;
11849 u32 ctxt = rcd->ctxt;
11856 adjust_rcv_timeout(rcd, npkts);
11868 u32 hdrqempty(struct hfi1_ctxtdata *rcd)
11872 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11875 if (hfi1_rcvhdrtail_kvaddr(rcd))
11876 tail = get_rcvhdrtail(rcd);
11878 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
11998 struct hfi1_ctxtdata *rcd)
12004 if (!rcd)
12007 ctxt = rcd->ctxt;
12017 rcd->rcvhdrq_dma);
12018 if (hfi1_rcvhdrtail_kvaddr(rcd))
12020 rcd->rcvhdrqtailaddr_dma);
12021 hfi1_set_seq_cnt(rcd, 1);
12024 hfi1_set_rcd_head(rcd, 0);
12030 * E.g. a rcd restart before the receive header wrapped.
12032 memset(rcd->rcvhdrq, 0, rcvhdrq_size(rcd));
12035 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr;
12042 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size)
12054 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT)
12057 (((rcd->eager_base >> RCV_SHIFT)
12064 * rcd->expected_count is set to individual RcvArray entries,
12068 reg = (((rcd->expected_count >> RCV_SHIFT)
12071 (((rcd->expected_base >> RCV_SHIFT)
12095 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt,
12096 IS_RCVAVAIL_START + rcd->ctxt, true);
12100 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt,
12101 IS_RCVAVAIL_START + rcd->ctxt, false);
12104 if ((op & HFI1_RCVCTRL_TAILUPD_ENB) && hfi1_rcvhdrtail_kvaddr(rcd))
12134 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt,
12135 IS_RCVURGENT_START + rcd->ctxt, true);
12137 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt,
12138 IS_RCVURGENT_START + rcd->ctxt, false);
12167 (u64)rcd->rcvavail_timeout <<
14765 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd,
14771 if (!rcd || !rcd->sc)
14774 hw_ctxt = rcd->sc->hw_context;
14779 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY))
14795 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, reg);
14800 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
14805 if (!rcd || !rcd->sc)
14808 hw_ctxt = rcd->sc->hw_context;
14821 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, 0);
14826 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd,
14832 if (!rcd || !rcd->sc)
14835 hw_ctxt = rcd->sc->hw_context;