Lines Matching defs:mask
1075 u32 mask; /* mask CSR offset */
5224 u64 mask;
5228 mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64)));
5229 return !(mask & BIT_ULL(bit));
5824 u64 mask = 1ULL << shift;
5828 handled |= mask;
5833 handled |= mask;
5835 reg_copy &= ~mask;
5879 * and can't be fixed, so mask the error bits.
5899 u64 mask;
5907 mask = read_kctxt_csr(dd, context, eri->mask);
5908 mask &= ~reg;
5909 write_kctxt_csr(dd, context, eri->mask, mask);
7220 * Convert an OPA Port LTP mask to capability mask
7237 * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7577 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
8969 u32 mask;
8971 mask = (HOST_INTERFACE_VERSION_MASK << HOST_INTERFACE_VERSION_SHIFT);
8974 frame &= ~mask;
9111 /* no need to mask, all variable sizes match field widths */
9237 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
9470 u64 mask;
9488 mask = read_csr(dd, dd->hfi1_id ?
9490 if (!(mask & QSFP_HFI0_INT_N))
9504 u64 mask;
9506 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
9514 mask |= (u64)QSFP_HFI0_INT_N;
9516 mask &= ~(u64)QSFP_HFI0_INT_N;
9518 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9524 u64 mask, qsfp_mask;
9530 mask = (u64)QSFP_HFI0_RESET_N;
9534 qsfp_mask &= ~mask;
9540 qsfp_mask |= mask;
10175 u32 mask = ~((1U << ppd->lmc) - 1);
10188 ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK)
10195 sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) <<
10197 (((lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) <<
10207 sdma_update_lmc(dd, mask, lid);
10311 dd_dev_err(dd, " passing lane mask: 0x%x", lanes);
11150 * NOTE: The low priority shift and mask are used here, but
11356 /* spin until the given per-VL status mask bits clear */
11357 static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask,
11365 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
11375 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
11376 which, VL_STATUS_CLEAR_TIMEOUT, mask, reg);
13270 /* clear from the handled mask of the general interrupt */
13329 /* mask all interrupts */
13335 /* reset general handler mask, chip MSI-X mappings */
14049 /* mask all interrupt sources */
14775 reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */
14960 u64 mask;
14963 mask = read_csr(dd, CCE_INT_MASK);
14981 /* Restore the interrupt mask */
14983 write_csr(dd, CCE_INT_MASK, mask);
14987 write_csr(dd, CCE_INT_MASK, mask);