Lines Matching defs:ctxt
5225 u32 is = IS_RCVURGENT_START + rcd->ctxt;
8393 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8483 WARN_ONCE(1, "Napi IRQ handler without napi set up ctxt=%d\n",
8484 rcd->ctxt);
11839 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
11849 u32 ctxt = rcd->ctxt;
11860 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg);
11865 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11872 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11878 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
11970 * @ctxt: the context
11974 void set_hdrq_regs(struct hfi1_devdata *dd, u8 ctxt, u8 entsize, u16 hdrcnt)
11980 write_kctxt_csr(dd, ctxt, RCV_HDR_CNT, reg);
11984 write_kctxt_csr(dd, ctxt, RCV_HDR_ENT_SIZE, reg);
11987 write_kctxt_csr(dd, ctxt, RCV_HDR_SIZE, reg);
11993 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
12002 u16 ctxt;
12007 ctxt = rcd->ctxt;
12009 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
12011 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
12016 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
12019 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
12047 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0);
12051 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0);
12060 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg);
12074 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg);
12075 if (ctxt == HFI1_CTRL_CTXT)
12086 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
12095 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt,
12096 IS_RCVAVAIL_START + rcd->ctxt, true);
12100 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt,
12101 IS_RCVAVAIL_START + rcd->ctxt, false);
12134 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt,
12135 IS_RCVURGENT_START + rcd->ctxt, true);
12137 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt,
12138 IS_RCVURGENT_START + rcd->ctxt, false);
12140 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx", ctxt, rcvctrl);
12141 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcvctrl);
12146 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
12148 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n",
12149 ctxt, reg);
12150 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
12151 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10);
12152 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00);
12153 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
12154 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
12155 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n",
12156 ctxt, reg, reg == 0 ? "not" : "still");
12166 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT,
12172 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
12181 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
14194 u64 ctxt = first_ctxt;
14197 reg |= ctxt << (8 * (i % 8));
14198 ctxt++;
14199 if (ctxt > last_ctxt)
14200 ctxt = first_ctxt;
14370 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
14387 for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) {
14390 for (qpn = 0, tctxt = ctxt;
14404 if (tctxt == ctxt + krcvqs[i])
14405 tctxt = ctxt;
14407 ctxt += krcvqs[i];
14548 reg |= (u64)hfi1_netdev_get_ctxt(dd, ctx_id++)->ctxt << (j * 8);
14795 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, reg);
14821 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, 0);
14847 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt)
14852 if (!ctxt || !ctxt->sc)
14855 hw_ctxt = ctxt->sc->hw_context;