Lines Matching defs:clear
1068 * "clear down" routine used for all second tier error interrupt register.
1074 u32 clear; /* clear CSR offset */
5683 /* clear down all observed info as quickly as possible after read */
5865 * The maximum number of times the error clear down will loop before
5894 write_kctxt_csr(dd, context, eri->clear, reg);
5941 * clear-down mechanism cannot be used because we cannot clear the
6480 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6713 static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear)
6721 rcvctrl &= ~clear;
6731 static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear)
6733 adjust_rcvctrl(dd, 0, clear);
6796 /* waiting until all indicators are clear */
6893 * Unfreeze the hardware - clear the freeze, wait for each
6894 * block's frozen bit to clear, then clear the frozen flag.
7503 /* set (14b only) or clear sideband credit */
8298 /* phase 1: scan and clear all handled interrupts */
8306 /* only clear if anything is set */
8340 /* clear the interrupt(s) */
8355 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8432 * Hold IRQs so we can safely clear the interrupt and
8434 * check and the interrupt clear. If a packet arrived, force another
8562 /* clear current state, set new state */
9351 /* reset our fabric serdes to clear any lingering problems */
10743 /* clear old transient LINKINIT_REASON code */
11356 /* spin until the given per-VL status mask bits clear */
11375 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
13176 * read_mod_write() - Calculate the IRQ register index and set/clear the bits
13179 * @bits: the bits to set or clear
13180 * @set: true == set the bits, false == clear the bits
13202 * @first: first IRQ source to set/clear
13203 * @last: last IRQ source (inclusive) to set/clear
13204 * @set: true == set the bits, false == clear the bits
13270 /* clear from the handled mask of the general interrupt */
13332 /* clear all pending interrupts */
13597 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13610 /* clear the condition */
13613 /* wait for the condition to clear */
13621 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
13636 /* CCE_CTRL - bits clear automatically */
13637 /* CCE_STATUS read-only, use CceCtrl to clear */
13688 /* init RSA engine to clear lingering errors */
13830 * clear.
13902 /* this is a clear-down */
14054 * DC Reset: do a full DC reset before the register clear.
14057 * across the clear.
14098 /* clear the DC reset */
14640 /* only actually clear the rule if it's the last user asking to do so */