Lines Matching defs:edev
72 static u32 efa_com_reg_read32(struct efa_com_dev *edev, u16 offset)
74 struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
91 writel(mmio_read_reg, edev->reg_bar + EFA_REGS_MMIO_REG_READ_OFF);
102 edev->efa_dev,
112 edev->efa_dev,
124 static int efa_com_admin_init_sq(struct efa_com_dev *edev)
126 struct efa_com_admin_queue *aq = &edev->aq;
144 sq->db_addr = (u32 __iomem *)(edev->reg_bar + EFA_REGS_AQ_PROD_DB_OFF);
149 writel(addr_low, edev->reg_bar + EFA_REGS_AQ_BASE_LO_OFF);
150 writel(addr_high, edev->reg_bar + EFA_REGS_AQ_BASE_HI_OFF);
156 writel(aq_caps, edev->reg_bar + EFA_REGS_AQ_CAPS_OFF);
161 static int efa_com_admin_init_cq(struct efa_com_dev *edev)
163 struct efa_com_admin_queue *aq = &edev->aq;
183 writel(addr_low, edev->reg_bar + EFA_REGS_ACQ_BASE_LO_OFF);
184 writel(addr_high, edev->reg_bar + EFA_REGS_ACQ_BASE_HI_OFF);
192 writel(acq_caps, edev->reg_bar + EFA_REGS_ACQ_CAPS_OFF);
197 static int efa_com_admin_init_aenq(struct efa_com_dev *edev,
200 struct efa_com_aenq *aenq = &edev->aenq;
206 ibdev_err(edev->efa_dev, "aenq handlers pointer is NULL\n");
211 aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr,
224 writel(addr_low, edev->reg_bar + EFA_REGS_AENQ_BASE_LO_OFF);
225 writel(addr_high, edev->reg_bar + EFA_REGS_AENQ_BASE_HI_OFF);
232 writel(aenq_caps, edev->reg_bar + EFA_REGS_AENQ_CAPS_OFF);
238 writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);
657 * @edev: EFA communication layer struct
659 void efa_com_admin_destroy(struct efa_com_dev *edev)
661 struct efa_com_admin_queue *aq = &edev->aq;
662 struct efa_com_aenq *aenq = &edev->aenq;
669 devm_kfree(edev->dmadev, aq->comp_ctx_pool);
670 devm_kfree(edev->dmadev, aq->comp_ctx);
673 dma_free_coherent(edev->dmadev, size, sq->entries, sq->dma_addr);
676 dma_free_coherent(edev->dmadev, size, cq->entries, cq->dma_addr);
679 dma_free_coherent(edev->dmadev, size, aenq->entries, aenq->dma_addr);
684 * @edev: EFA communication layer struct
689 void efa_com_set_admin_polling_mode(struct efa_com_dev *edev, bool polling)
696 writel(mask_value, edev->reg_bar + EFA_REGS_INTR_MASK_OFF);
698 set_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state);
700 clear_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state);
703 static void efa_com_stats_init(struct efa_com_dev *edev)
705 atomic64_t *s = (atomic64_t *)&edev->aq.stats;
708 for (i = 0; i < sizeof(edev->aq.stats) / sizeof(*s); i++, s++)
714 * @edev: EFA communication layer struct
722 int efa_com_admin_init(struct efa_com_dev *edev,
725 struct efa_com_admin_queue *aq = &edev->aq;
731 dev_sts = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF);
733 ibdev_err(edev->efa_dev,
740 aq->dmadev = edev->dmadev;
741 aq->efa_dev = edev->efa_dev;
746 efa_com_stats_init(edev);
752 err = efa_com_admin_init_sq(edev);
756 err = efa_com_admin_init_cq(edev);
760 efa_com_set_admin_polling_mode(edev, false);
762 err = efa_com_admin_init_aenq(edev, aenq_handlers);
766 cap = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF);
781 dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->cq.entries),
784 dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->sq.entries),
787 devm_kfree(edev->dmadev, aq->comp_ctx);
794 * @edev: EFA communication layer struct
801 void efa_com_admin_q_comp_intr_handler(struct efa_com_dev *edev)
805 spin_lock_irqsave(&edev->aq.cq.lock, flags);
806 efa_com_handle_admin_completion(&edev->aq);
807 spin_unlock_irqrestore(&edev->aq.cq.lock, flags);
814 static efa_aenq_handler efa_com_get_specific_aenq_cb(struct efa_com_dev *edev,
817 struct efa_aenq_handlers *aenq_handlers = edev->aenq.aenq_handlers;
827 * @edev: EFA communication layer struct
832 void efa_com_aenq_intr_handler(struct efa_com_dev *edev, void *data)
835 struct efa_com_aenq *aenq = &edev->aenq;
857 handler_cb = efa_com_get_specific_aenq_cb(edev,
881 writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);
884 static void efa_com_mmio_reg_read_resp_addr_init(struct efa_com_dev *edev)
886 struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
894 writel(addr_high, edev->reg_bar + EFA_REGS_MMIO_RESP_HI_OFF);
895 writel(addr_low, edev->reg_bar + EFA_REGS_MMIO_RESP_LO_OFF);
898 int efa_com_mmio_reg_read_init(struct efa_com_dev *edev)
900 struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
904 dma_alloc_coherent(edev->dmadev, sizeof(*mmio_read->read_resp),
909 efa_com_mmio_reg_read_resp_addr_init(edev);
918 void efa_com_mmio_reg_read_destroy(struct efa_com_dev *edev)
920 struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
922 dma_free_coherent(edev->dmadev, sizeof(*mmio_read->read_resp),
926 int efa_com_validate_version(struct efa_com_dev *edev)
938 ver = efa_com_reg_read32(edev, EFA_REGS_VERSION_OFF);
939 ctrl_ver = efa_com_reg_read32(edev,
942 ibdev_dbg(edev->efa_dev, "efa device version: %d.%d\n",
951 ibdev_err(edev->efa_dev,
957 edev->efa_dev,
979 ibdev_err(edev->efa_dev,
990 * @edev: EFA communication layer struct
996 int efa_com_get_dma_width(struct efa_com_dev *edev)
998 u32 caps = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF);
1003 ibdev_dbg(edev->efa_dev, "DMA width: %d\n", width);
1006 ibdev_err(edev->efa_dev, "DMA width illegal value: %d\n", width);
1010 edev->dma_addr_bits = width;
1015 static int wait_for_reset_state(struct efa_com_dev *edev, u32 timeout, int on)
1020 val = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF);
1025 ibdev_dbg(edev->efa_dev, "Reset indication val %d\n", val);
1034 * @edev: EFA communication layer struct
1039 int efa_com_dev_reset(struct efa_com_dev *edev,
1046 stat = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF);
1047 cap = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF);
1050 ibdev_err(edev->efa_dev,
1057 ibdev_err(edev->efa_dev, "Invalid timeout value\n");
1064 writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);
1067 efa_com_mmio_reg_read_resp_addr_init(edev);
1069 err = wait_for_reset_state(edev, timeout, 1);
1071 ibdev_err(edev->efa_dev, "Reset indication didn't turn on\n");
1076 writel(0, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);
1077 err = wait_for_reset_state(edev, timeout, 0);
1079 ibdev_err(edev->efa_dev, "Reset indication didn't turn off\n");
1086 edev->aq.completion_timeout = timeout * 100000;
1088 edev->aq.completion_timeout = ADMIN_CMD_TIMEOUT_US;
1093 static int efa_com_create_eq(struct efa_com_dev *edev,
1097 struct efa_com_admin_queue *aq = &edev->aq;
1118 ibdev_err_ratelimited(edev->efa_dev,
1128 static void efa_com_destroy_eq(struct efa_com_dev *edev,
1131 struct efa_com_admin_queue *aq = &edev->aq;
1145 ibdev_err_ratelimited(edev->efa_dev,
1150 static void efa_com_arm_eq(struct efa_com_dev *edev, struct efa_com_eq *eeq)
1157 writel(val, edev->reg_bar + EFA_REGS_EQ_DB_OFF);
1160 void efa_com_eq_comp_intr_handler(struct efa_com_dev *edev,
1196 efa_com_arm_eq(eeq->edev, eeq);
1199 void efa_com_eq_destroy(struct efa_com_dev *edev, struct efa_com_eq *eeq)
1205 efa_com_destroy_eq(edev, ¶ms);
1206 dma_free_coherent(edev->dmadev, eeq->depth * sizeof(*eeq->eqes),
1210 int efa_com_eq_init(struct efa_com_dev *edev, struct efa_com_eq *eeq,
1223 eeq->eqes = dma_alloc_coherent(edev->dmadev,
1229 err = efa_com_create_eq(edev, ¶ms, &result);
1234 eeq->edev = edev;
1239 efa_com_arm_eq(edev, eeq);
1244 dma_free_coherent(edev->dmadev, params.depth * sizeof(*eeq->eqes),