Lines Matching defs:aenq
200 struct efa_com_aenq *aenq = &edev->aenq;
206 ibdev_err(edev->efa_dev, "aenq handlers pointer is NULL\n");
210 size = EFA_ASYNC_QUEUE_DEPTH * sizeof(*aenq->entries);
211 aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr,
213 if (!aenq->entries)
216 aenq->aenq_handlers = aenq_handlers;
217 aenq->depth = EFA_ASYNC_QUEUE_DEPTH;
218 aenq->cc = 0;
219 aenq->phase = 1;
221 addr_low = lower_32_bits(aenq->dma_addr);
222 addr_high = upper_32_bits(aenq->dma_addr);
227 EFA_SET(&aenq_caps, EFA_REGS_AENQ_CAPS_AENQ_DEPTH, aenq->depth);
231 aenq->msix_vector_idx);
238 writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);
662 struct efa_com_aenq *aenq = &edev->aenq;
678 size = aenq->depth * sizeof(*aenq->entries);
679 dma_free_coherent(edev->dmadev, size, aenq->entries, aenq->dma_addr);
817 struct efa_aenq_handlers *aenq_handlers = edev->aenq.aenq_handlers;
830 * Go over the async event notification queue and call the proper aenq handler.
835 struct efa_com_aenq *aenq = &edev->aenq;
842 ci = aenq->cc & (aenq->depth - 1);
843 phase = aenq->phase;
844 aenq_e = &aenq->entries[ci]; /* Get first entry */
865 if (ci == aenq->depth) {
869 aenq_e = &aenq->entries[ci];
873 aenq->cc += processed;
874 aenq->phase = phase;
876 /* Don't update aenq doorbell if there weren't any processed events */
881 writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);