Lines Matching refs:data
169 struct mcp4131_data *data = iio_priv(indio_dev);
174 mutex_lock(&data->lock);
176 data->buf[0] = (address << MCP4131_WIPER_SHIFT) | MCP4131_READ;
177 data->buf[1] = 0;
179 err = mcp4131_read(data->spi, data->buf, 2);
181 mutex_unlock(&data->lock);
186 if (!MCP4131_CMDERR(data->buf)) {
187 mutex_unlock(&data->lock);
191 *val = MCP4131_RAW(data->buf);
192 mutex_unlock(&data->lock);
197 *val = 1000 * data->cfg->kohms;
198 *val2 = data->cfg->max_pos;
210 struct mcp4131_data *data = iio_priv(indio_dev);
215 if (val > data->cfg->max_pos || val < 0)
223 mutex_lock(&data->lock);
225 data->buf[0] = address << MCP4131_WIPER_SHIFT;
226 data->buf[0] |= MCP4131_WRITE | (val >> 8);
227 data->buf[1] = val & 0xFF; /* 8 bits here */
229 err = spi_write(data->spi, data->buf, 2);
230 mutex_unlock(&data->lock);
245 struct mcp4131_data *data;
248 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
252 data = iio_priv(indio_dev);
254 data->spi = spi;
255 data->cfg = device_get_match_data(&spi->dev);
256 if (!data->cfg) {
258 data->cfg = &mcp4131_cfg[devid];
261 mutex_init(&data->lock);
265 indio_dev->num_channels = data->cfg->wipers;
279 .data = &mcp4131_cfg[MCP413x_502] },
281 .data = &mcp4131_cfg[MCP413x_103] },
283 .data = &mcp4131_cfg[MCP413x_503] },
285 .data = &mcp4131_cfg[MCP413x_104] },
287 .data = &mcp4131_cfg[MCP413x_502] },
289 .data = &mcp4131_cfg[MCP413x_103] },
291 .data = &mcp4131_cfg[MCP413x_503] },
293 .data = &mcp4131_cfg[MCP413x_104] },
295 .data = &mcp4131_cfg[MCP414x_502] },
297 .data = &mcp4131_cfg[MCP414x_103] },
299 .data = &mcp4131_cfg[MCP414x_503] },
301 .data = &mcp4131_cfg[MCP414x_104] },
303 .data = &mcp4131_cfg[MCP414x_502] },
305 .data = &mcp4131_cfg[MCP414x_103] },
307 .data = &mcp4131_cfg[MCP414x_503] },
309 .data = &mcp4131_cfg[MCP414x_104] },
311 .data = &mcp4131_cfg[MCP415x_502] },
313 .data = &mcp4131_cfg[MCP415x_103] },
315 .data = &mcp4131_cfg[MCP415x_503] },
317 .data = &mcp4131_cfg[MCP415x_104] },
319 .data = &mcp4131_cfg[MCP415x_502] },
321 .data = &mcp4131_cfg[MCP415x_103] },
323 .data = &mcp4131_cfg[MCP415x_503] },
325 .data = &mcp4131_cfg[MCP415x_104] },
327 .data = &mcp4131_cfg[MCP416x_502] },
329 .data = &mcp4131_cfg[MCP416x_103] },
331 .data = &mcp4131_cfg[MCP416x_503] },
333 .data = &mcp4131_cfg[MCP416x_104] },
335 .data = &mcp4131_cfg[MCP416x_502] },
337 .data = &mcp4131_cfg[MCP416x_103] },
339 .data = &mcp4131_cfg[MCP416x_503] },
341 .data = &mcp4131_cfg[MCP416x_104] },
343 .data = &mcp4131_cfg[MCP423x_502] },
345 .data = &mcp4131_cfg[MCP423x_103] },
347 .data = &mcp4131_cfg[MCP423x_503] },
349 .data = &mcp4131_cfg[MCP423x_104] },
351 .data = &mcp4131_cfg[MCP423x_502] },
353 .data = &mcp4131_cfg[MCP423x_103] },
355 .data = &mcp4131_cfg[MCP423x_503] },
357 .data = &mcp4131_cfg[MCP423x_104] },
359 .data = &mcp4131_cfg[MCP424x_502] },
361 .data = &mcp4131_cfg[MCP424x_103] },
363 .data = &mcp4131_cfg[MCP424x_503] },
365 .data = &mcp4131_cfg[MCP424x_104] },
367 .data = &mcp4131_cfg[MCP424x_502] },
369 .data = &mcp4131_cfg[MCP424x_103] },
371 .data = &mcp4131_cfg[MCP424x_503] },
373 .data = &mcp4131_cfg[MCP424x_104] },
375 .data = &mcp4131_cfg[MCP425x_502] },
377 .data = &mcp4131_cfg[MCP425x_103] },
379 .data = &mcp4131_cfg[MCP425x_503] },
381 .data = &mcp4131_cfg[MCP425x_104] },
383 .data = &mcp4131_cfg[MCP425x_502] },
385 .data = &mcp4131_cfg[MCP425x_103] },
387 .data = &mcp4131_cfg[MCP425x_503] },
389 .data = &mcp4131_cfg[MCP425x_104] },
391 .data = &mcp4131_cfg[MCP426x_502] },
393 .data = &mcp4131_cfg[MCP426x_103] },
395 .data = &mcp4131_cfg[MCP426x_503] },
397 .data = &mcp4131_cfg[MCP426x_104] },
399 .data = &mcp4131_cfg[MCP426x_502] },
401 .data = &mcp4131_cfg[MCP426x_103] },
403 .data = &mcp4131_cfg[MCP426x_503] },
405 .data = &mcp4131_cfg[MCP426x_104] },