Lines Matching defs:AD9523_R1B
28 #define AD9523_R1B (1 << 16)
33 #define AD9523_SERIAL_PORT_CONFIG (AD9523_R1B | 0x0)
34 #define AD9523_VERSION_REGISTER (AD9523_R1B | 0x2)
35 #define AD9523_PART_REGISTER (AD9523_R1B | 0x3)
36 #define AD9523_READBACK_CTRL (AD9523_R1B | 0x4)
42 #define AD9523_PLL1_REF_TEST_DIVIDER (AD9523_R1B | 0x14)
45 #define AD9523_PLL1_INPUT_RECEIVERS_CTRL (AD9523_R1B | 0x1A)
46 #define AD9523_PLL1_REF_CTRL (AD9523_R1B | 0x1B)
47 #define AD9523_PLL1_MISC_CTRL (AD9523_R1B | 0x1C)
48 #define AD9523_PLL1_LOOP_FILTER_CTRL (AD9523_R1B | 0x1D)
50 #define AD9523_PLL2_CHARGE_PUMP (AD9523_R1B | 0xF0)
51 #define AD9523_PLL2_FEEDBACK_DIVIDER_AB (AD9523_R1B | 0xF1)
52 #define AD9523_PLL2_CTRL (AD9523_R1B | 0xF2)
53 #define AD9523_PLL2_VCO_CTRL (AD9523_R1B | 0xF3)
54 #define AD9523_PLL2_VCO_DIVIDER (AD9523_R1B | 0xF4)
56 #define AD9523_PLL2_R2_DIVIDER (AD9523_R1B | 0xF7)
60 #define AD9523_PLL1_OUTPUT_CTRL (AD9523_R1B | 0x1BA)
61 #define AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B | 0x1BB)
63 #define AD9523_READBACK_0 (AD9523_R1B | 0x22C)
64 #define AD9523_READBACK_1 (AD9523_R1B | 0x22D)
67 #define AD9523_POWER_DOWN_CTRL (AD9523_R1B | 0x233)
68 #define AD9523_IO_UPDATE (AD9523_R1B | 0x234)
70 #define AD9523_EEPROM_DATA_XFER_STATUS (AD9523_R1B | 0xB00)
71 #define AD9523_EEPROM_ERROR_READBACK (AD9523_R1B | 0xB01)
72 #define AD9523_EEPROM_CTRL1 (AD9523_R1B | 0xB02)
73 #define AD9523_EEPROM_CTRL2 (AD9523_R1B | 0xB03)
734 ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval);
737 ret = ad9523_read(indio_dev, reg | AD9523_R1B);