Lines Matching refs:addr
292 /* 0 -> reg addr, 1->ch0 mask, 2->ch1 mask */
316 static u8 _ad3552r_reg_len(u8 addr)
318 switch (addr) {
330 if (addr > AD3552R_REG_ADDR_HW_LDAC_24B)
332 if (addr > AD3552R_REG_ADDR_HW_LDAC_16B)
339 static int ad3552r_transfer(struct ad3552r_desc *dac, u8 addr, u32 len,
345 buf[0] = addr & AD3552R_ADDR_MASK;
354 static int ad3552r_write_reg(struct ad3552r_desc *dac, u8 addr, u16 val)
359 reg_len = _ad3552r_reg_len(addr);
369 return ad3552r_transfer(dac, addr, reg_len, buf, false);
372 static int ad3552r_read_reg(struct ad3552r_desc *dac, u8 addr, u16 *val)
377 reg_len = _ad3552r_reg_len(addr);
378 err = ad3552r_transfer(dac, addr, reg_len, buf, true);
397 static int ad3552r_update_reg_field(struct ad3552r_desc *dac, u8 addr, u16 mask,
403 ret = ad3552r_read_reg(dac, addr, ®);
410 return ad3552r_write_reg(dac, addr, reg);
531 u8 addr, buff[AD3552R_NUM_CH * AD3552R_MAX_REG_SIZE + 1];
533 addr = AD3552R_REG_ADDR_CH_INPUT_24B(1);
546 err = ad3552r_transfer(dac, addr, len, buff, false);
559 u8 addr, buff[AD3552R_MAX_REG_SIZE];
565 addr = AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B;
567 addr = AD3552R_REG_ADDR_CH_INPUT_24B(__ffs(mask));
572 err = ad3552r_transfer(dac, addr, 3, data, false);
640 u8 addr;
643 static int ad3552r_read_reg_wrapper(struct reg_addr_pool *addr)
648 err = ad3552r_read_reg(addr->dac, addr->addr, &val);
657 struct reg_addr_pool addr;
682 addr.dac = dac;
683 addr.addr = AD3552R_REG_ADDR_INTERFACE_CONFIG_B;
684 ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
695 ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
807 u8 addr;
855 addr = AD3552R_REG_ADDR_CH_GAIN(ch);
856 err = ad3552r_write_reg(dac, addr,
863 err = ad3552r_write_reg(dac, addr, reg);