Lines Matching defs:ams
263 * struct ams - This structure contains necessary state for xilinx-ams to operate
277 struct ams {
291 static inline void ams_ps_update_reg(struct ams *ams, unsigned int offset,
296 val = readl(ams->ps_base + offset);
298 writel(regval, ams->ps_base + offset);
301 static inline void ams_pl_update_reg(struct ams *ams, unsigned int offset,
306 val = readl(ams->pl_base + offset);
308 writel(regval, ams->pl_base + offset);
311 static void ams_update_intrmask(struct ams *ams, u64 mask, u64 val)
315 ams->intr_mask = (ams->intr_mask & ~mask) | (val & mask);
317 regval = ~(ams->intr_mask | ams->current_masked_alarm);
318 writel(regval, ams->base + AMS_IER_0);
320 regval = ~(FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask));
321 writel(regval, ams->base + AMS_IER_1);
323 regval = ams->intr_mask | ams->current_masked_alarm;
324 writel(regval, ams->base + AMS_IDR_0);
326 regval = FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask);
327 writel(regval, ams->base + AMS_IDR_1);
330 static void ams_disable_all_alarms(struct ams *ams)
333 if (ams->ps_base) {
334 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK,
336 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK,
341 if (ams->pl_base) {
342 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK,
344 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK,
349 static void ams_update_ps_alarm(struct ams *ams, unsigned long alarm_mask)
360 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg);
364 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg);
367 static void ams_update_pl_alarm(struct ams *ams, unsigned long alarm_mask)
381 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg);
385 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg);
388 static void ams_update_alarm(struct ams *ams, unsigned long alarm_mask)
392 if (ams->ps_base)
393 ams_update_ps_alarm(ams, alarm_mask);
395 if (ams->pl_base)
396 ams_update_pl_alarm(ams, alarm_mask);
398 spin_lock_irqsave(&ams->intr_lock, flags);
399 ams_update_intrmask(ams, AMS_ISR0_ALARM_MASK, ~alarm_mask);
400 spin_unlock_irqrestore(&ams->intr_lock, flags);
405 struct ams *ams = iio_priv(indio_dev);
420 if (ams->ps_base) {
422 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
427 writel(regval, ams->ps_base + AMS_REG_SEQ_CH0);
430 writel(regval, ams->ps_base + AMS_REG_SEQ_CH2);
433 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
437 if (ams->pl_base) {
439 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
446 writel(regval, ams->pl_base + AMS_REG_SEQ_CH0);
449 writel(regval, ams->pl_base + AMS_REG_SEQ_CH1);
452 writel(regval, ams->pl_base + AMS_REG_SEQ_CH2);
455 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
460 static int ams_init_device(struct ams *ams)
467 if (ams->ps_base) {
468 writel(AMS_PS_RESET_VALUE, ams->ps_base + AMS_VP_VN);
470 ret = readl_poll_timeout(ams->base + AMS_PS_CSTS, reg, (reg & expect),
476 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
480 if (ams->pl_base) {
481 value = readl(ams->base + AMS_PL_CSTS);
485 writel(AMS_PL_RESET_VALUE, ams->pl_base + AMS_VP_VN);
488 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
492 ams_disable_all_alarms(ams);
495 ams_update_intrmask(ams, AMS_ALARM_MASK, AMS_ALARM_MASK);
498 writel(AMS_ISR0_ALARM_MASK, ams->base + AMS_ISR_0);
499 writel(AMS_ISR1_ALARM_MASK, ams->base + AMS_ISR_1);
504 static int ams_enable_single_channel(struct ams *ams, unsigned int offset)
535 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
539 ams_ps_update_reg(ams, AMS_REG_CONFIG0, AMS_CONF0_CHANNEL_NUM_MASK,
543 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
549 static int ams_read_vcc_reg(struct ams *ams, unsigned int offset, u32 *data)
555 ret = ams_enable_single_channel(ams, offset);
560 writel(expect, ams->base + AMS_ISR_1);
561 ret = readl_poll_timeout(ams->base + AMS_ISR_1, reg, (reg & expect),
566 *data = readl(ams->base + offset);
599 static int ams_get_pl_scale(struct ams *ams, int address)
616 regval = readl(ams->pl_base + AMS_REG_CONFIG4);
623 regval = readl(ams->pl_base + AMS_REG_CONFIG4);
630 regval = readl(ams->pl_base + AMS_REG_CONFIG4);
637 regval = readl(ams->pl_base + AMS_REG_CONFIG4);
681 struct ams *ams = iio_priv(indio_dev);
686 mutex_lock(&ams->lock);
688 ret = ams_read_vcc_reg(ams, chan->address, val);
693 *val = readl(ams->pl_base + chan->address);
695 *val = readl(ams->ps_base + chan->address);
699 mutex_unlock(&ams->lock);
708 *val = ams_get_pl_scale(ams, chan->address);
885 struct ams *ams = iio_priv(indio_dev);
887 return !!(ams->alarm_mask & ams_get_alarm_mask(chan->scan_index));
896 struct ams *ams = iio_priv(indio_dev);
901 mutex_lock(&ams->lock);
904 ams->alarm_mask |= alarm;
906 ams->alarm_mask &= ~alarm;
908 ams_update_alarm(ams, ams->alarm_mask);
910 mutex_unlock(&ams->lock);
921 struct ams *ams = iio_priv(indio_dev);
924 mutex_lock(&ams->lock);
927 *val = readl(ams->pl_base + offset);
929 *val = readl(ams->ps_base + offset);
931 mutex_unlock(&ams->lock);
942 struct ams *ams = iio_priv(indio_dev);
945 mutex_lock(&ams->lock);
952 ams_pl_update_reg(ams, offset,
956 ams_ps_update_reg(ams, offset,
963 writel(val, ams->pl_base + offset);
965 writel(val, ams->ps_base + offset);
967 mutex_unlock(&ams->lock);
1011 * ams_unmask_worker - ams alarm interrupt unmask worker
1023 struct ams *ams = container_of(work, struct ams, ams_unmask_work.work);
1026 spin_lock_irq(&ams->intr_lock);
1028 status = readl(ams->base + AMS_ISR_0);
1031 unmask = (ams->current_masked_alarm ^ status) & ams->current_masked_alarm;
1034 unmask |= ams->intr_mask;
1036 ams->current_masked_alarm &= status;
1039 ams->current_masked_alarm &= ~ams->intr_mask;
1042 writel(unmask, ams->base + AMS_ISR_0);
1044 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK);
1046 spin_unlock_irq(&ams->intr_lock);
1049 if (ams->current_masked_alarm)
1050 schedule_delayed_work(&ams->ams_unmask_work,
1057 struct ams *ams = iio_priv(indio_dev);
1060 spin_lock(&ams->intr_lock);
1062 isr0 = readl(ams->base + AMS_ISR_0);
1065 isr0 &= ~((ams->intr_mask & AMS_ISR0_ALARM_MASK) | ams->current_masked_alarm);
1067 spin_unlock(&ams->intr_lock);
1072 writel(isr0, ams->base + AMS_ISR_0);
1075 ams->current_masked_alarm |= isr0;
1076 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK);
1080 schedule_delayed_work(&ams->ams_unmask_work,
1083 spin_unlock(&ams->intr_lock);
1202 struct ams *ams = data;
1204 iounmap(ams->ps_base);
1209 struct ams *ams = data;
1211 iounmap(ams->pl_base);
1219 struct ams *ams = iio_priv(indio_dev);
1223 if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-ps")) {
1224 ams->ps_base = fwnode_iomap(fwnode, 0);
1225 if (!ams->ps_base)
1227 ret = devm_add_action_or_reset(dev, ams_iounmap_ps, ams);
1234 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-pl")) {
1235 ams->pl_base = fwnode_iomap(fwnode, 0);
1236 if (!ams->pl_base)
1239 ret = devm_add_action_or_reset(dev, ams_iounmap_pl, ams);
1248 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams")) {
1261 struct ams *ams = iio_priv(indio_dev);
1311 ams->pl_base + falling_off);
1313 ams->pl_base + rising_off);
1316 ams->ps_base + falling_off);
1318 ams->ps_base + rising_off);
1343 { .compatible = "xlnx,zynqmp-ams" },
1351 struct ams *ams;
1355 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ams));
1359 ams = iio_priv(indio_dev);
1360 mutex_init(&ams->lock);
1361 spin_lock_init(&ams->intr_lock);
1363 indio_dev->name = "xilinx-ams";
1368 ams->base = devm_platform_ioremap_resource(pdev, 0);
1369 if (IS_ERR(ams->base))
1370 return PTR_ERR(ams->base);
1372 ams->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1373 if (IS_ERR(ams->clk))
1374 return PTR_ERR(ams->clk);
1376 ret = devm_delayed_work_autocancel(&pdev->dev, &ams->ams_unmask_work,
1385 ret = ams_init_device(ams);
1395 ret = devm_request_irq(&pdev->dev, irq, &ams_irq, 0, "ams-irq",
1407 struct ams *ams = iio_priv(dev_get_drvdata(dev));
1409 clk_disable_unprepare(ams->clk);
1416 struct ams *ams = iio_priv(dev_get_drvdata(dev));
1418 return clk_prepare_enable(ams->clk);
1426 .name = "xilinx-ams",