Lines Matching refs:dma
26 #include <linux/dma-mapping.h>
43 struct tiadc_dma dma;
217 struct tiadc_dma *dma = &adc_dev->dma;
221 data = dma->buf + dma->current_period * dma->period_size;
222 dma->current_period = 1 - dma->current_period; /* swap the buffer ID */
224 for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) {
233 struct tiadc_dma *dma = &adc_dev->dma;
236 dma->current_period = 0; /* We start to fill period 0 */
245 dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1,
249 dma->period_size = rounddown(DMA_BUFFER_SIZE / 2,
250 (dma->fifo_thresh + 1) * sizeof(u16));
252 dma->conf.src_maxburst = dma->fifo_thresh + 1;
253 dmaengine_slave_config(dma->chan, &dma->conf);
255 desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr,
256 dma->period_size * 2,
257 dma->period_size, DMA_DEV_TO_MEM,
265 dma->cookie = dmaengine_submit(desc);
267 dma_async_issue_pending(dma->chan);
269 tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh);
270 tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh);
301 struct tiadc_dma *dma = &adc_dev->dma;
313 if (dma->chan)
323 if (!dma->chan)
333 struct tiadc_dma *dma = &adc_dev->dma;
342 if (dma->chan) {
344 dmaengine_terminate_async(dma->chan);
530 struct tiadc_dma *dma = &adc_dev->dma;
534 dma->conf.direction = DMA_DEV_TO_MEM;
535 dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
536 dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1;
542 dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1");
543 if (IS_ERR(dma->chan)) {
544 int ret = PTR_ERR(dma->chan);
546 dma->chan = NULL;
551 dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
552 &dma->addr, GFP_KERNEL);
553 if (!dma->buf)
559 dma_release_channel(dma->chan);
690 struct tiadc_dma *dma = &adc_dev->dma;
693 if (dma->chan) {
694 dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
695 dma->buf, dma->addr);
696 dma_release_channel(dma->chan);