Lines Matching defs:smpr
165 * @smpr: smpr1 & smpr2 registers offset array
184 const u32 smpr[2];
387 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */
398 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */
426 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 },
480 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */
491 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */
521 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 },
542 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 },
563 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 },
1261 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);
1262 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);
1424 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);
1425 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);
1926 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
1927 u32 period_ns, shift = smpr->shift, mask = smpr->mask;
1928 unsigned int i, smp, r = smpr->reg;