Lines Matching defs:adc
31 #include "stm32-adc-core.h"
122 * struct stm32_adc_calib - optional adc calibration data
238 * @clk: clock for this adc instance
239 * @irq: interrupt for this adc instance
572 * @adc: stm32 adc instance
573 * @reg: reg offset in adc instance
578 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
580 return readl_relaxed(adc->common->base + adc->offset + reg);
583 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
589 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
591 return readw_relaxed(adc->common->base + adc->offset + reg);
594 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
596 writel_relaxed(val, adc->common->base + adc->offset + reg);
599 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
603 spin_lock_irqsave(&adc->lock, flags);
604 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
605 spin_unlock_irqrestore(&adc->lock, flags);
608 static void stm32_adc_set_bits_common(struct stm32_adc *adc, u32 reg, u32 bits)
610 spin_lock(&adc->common->lock);
611 writel_relaxed(readl_relaxed(adc->common->base + reg) | bits,
612 adc->common->base + reg);
613 spin_unlock(&adc->common->lock);
616 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
620 spin_lock_irqsave(&adc->lock, flags);
621 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
622 spin_unlock_irqrestore(&adc->lock, flags);
625 static void stm32_adc_clr_bits_common(struct stm32_adc *adc, u32 reg, u32 bits)
627 spin_lock(&adc->common->lock);
628 writel_relaxed(readl_relaxed(adc->common->base + reg) & ~bits,
629 adc->common->base + reg);
630 spin_unlock(&adc->common->lock);
635 * @adc: stm32 adc instance
637 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
639 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg,
640 adc->cfg->regs->ier_eoc.mask);
645 * @adc: stm32 adc instance
647 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
649 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg,
650 adc->cfg->regs->ier_eoc.mask);
653 static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc)
655 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg,
656 adc->cfg->regs->ier_ovr.mask);
659 static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc)
661 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg,
662 adc->cfg->regs->ier_ovr.mask);
665 static void stm32_adc_set_res(struct stm32_adc *adc)
667 const struct stm32_adc_regs *res = &adc->cfg->regs->res;
670 val = stm32_adc_readl(adc, res->reg);
671 val = (val & ~res->mask) | (adc->res << res->shift);
672 stm32_adc_writel(adc, res->reg, val);
678 struct stm32_adc *adc = iio_priv(indio_dev);
680 if (adc->cfg->unprepare)
681 adc->cfg->unprepare(indio_dev);
683 clk_disable_unprepare(adc->clk);
691 struct stm32_adc *adc = iio_priv(indio_dev);
694 ret = clk_prepare_enable(adc->clk);
698 stm32_adc_set_res(adc);
700 if (adc->cfg->prepare) {
701 ret = adc->cfg->prepare(indio_dev);
709 clk_disable_unprepare(adc->clk);
716 struct stm32_adc *adc = iio_priv(indio_dev);
720 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE)
726 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcore.reg,
727 adc->cfg->regs->or_vddcore.mask);
731 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcpu.reg,
732 adc->cfg->regs->or_vddcpu.mask);
736 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddq_ddr.reg,
737 adc->cfg->regs->or_vddq_ddr.mask);
741 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vref.reg,
742 adc->cfg->regs->ccr_vref.mask);
746 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vbat.reg,
747 adc->cfg->regs->ccr_vbat.mask);
753 static void stm32_adc_int_ch_disable(struct stm32_adc *adc)
758 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE)
763 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcore.reg,
764 adc->cfg->regs->or_vddcore.mask);
767 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcpu.reg,
768 adc->cfg->regs->or_vddcpu.mask);
771 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddq_ddr.reg,
772 adc->cfg->regs->or_vddq_ddr.mask);
775 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vref.reg,
776 adc->cfg->regs->ccr_vref.mask);
779 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vbat.reg,
780 adc->cfg->regs->ccr_vbat.mask);
798 struct stm32_adc *adc = iio_priv(indio_dev);
800 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
803 stm32_adc_set_bits(adc, STM32F4_ADC_CR2,
806 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
812 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
813 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
818 struct stm32_adc *adc = iio_priv(indio_dev);
820 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
821 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
823 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
824 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2,
830 struct stm32_adc *adc = iio_priv(indio_dev);
832 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);
837 struct stm32_adc *adc = iio_priv(indio_dev);
847 spin_lock_irqsave(&adc->lock, flags);
848 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR);
850 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val);
851 spin_unlock_irqrestore(&adc->lock, flags);
853 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
858 struct stm32_adc *adc = iio_priv(indio_dev);
862 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP);
871 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
876 struct stm32_adc *adc = iio_priv(indio_dev);
878 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);
883 struct stm32_adc *adc = iio_priv(indio_dev);
886 stm32_adc_set_bits(adc, STM32H7_ADC_CFGR,
889 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
894 struct stm32_adc *adc = iio_priv(indio_dev);
899 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
900 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN);
902 if (adc->cfg->has_boostmode &&
903 adc->common->rate > STM32H7_BOOST_CLKRATE)
904 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
907 if (!adc->cfg->has_vregready) {
916 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
923 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc)
925 if (adc->cfg->has_boostmode)
926 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
929 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
934 struct stm32_adc *adc = iio_priv(indio_dev);
938 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
940 /* Poll for ADRDY to be set (after adc startup time) */
945 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
949 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
957 struct stm32_adc *adc = iio_priv(indio_dev);
961 if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN))
965 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
980 struct stm32_adc *adc = iio_priv(indio_dev);
988 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
999 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
1000 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK);
1001 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT;
1005 adc->cal.lincal_saved = true;
1017 struct stm32_adc *adc = iio_priv(indio_dev);
1028 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT;
1029 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val);
1030 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
1046 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
1054 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
1055 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) {
1090 struct stm32_adc *adc = iio_priv(indio_dev);
1095 if (adc->cfg->has_linearcal && do_lincal)
1105 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk);
1108 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
1123 stm32_adc_set_bits(adc, STM32H7_ADC_CR, msk);
1124 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
1135 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk);
1150 struct stm32_adc *adc = iio_priv(indio_dev);
1153 if (adc->cal.lincal_saved)
1160 val = stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_LINCALRDYW_MASK;
1180 struct stm32_adc *adc = iio_priv(indio_dev);
1188 if (adc->cfg->has_linearcal)
1198 stm32_adc_writel(adc, adc->cfg->regs->difsel.reg, adc->difsel);
1204 if (adc->cfg->has_linearcal) {
1205 if (!adc->cal.lincal_saved)
1214 if (adc->cfg->has_presel)
1215 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel);
1222 stm32_adc_int_ch_disable(adc);
1224 stm32h7_adc_enter_pwr_down(adc);
1231 struct stm32_adc *adc = iio_priv(indio_dev);
1233 if (adc->cfg->has_presel)
1234 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0);
1236 stm32_adc_int_ch_disable(adc);
1237 stm32h7_adc_enter_pwr_down(adc);
1254 struct stm32_adc *adc = iio_priv(indio_dev);
1255 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr;
1261 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);
1262 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);
1277 val = stm32_adc_readl(adc, sqr[i].reg);
1280 stm32_adc_writel(adc, sqr[i].reg, val);
1287 val = stm32_adc_readl(adc, sqr[0].reg);
1290 stm32_adc_writel(adc, sqr[0].reg, val);
1305 struct stm32_adc *adc = iio_priv(indio_dev);
1309 for (i = 0; adc->cfg->trigs[i].name; i++) {
1316 !strcmp(adc->cfg->trigs[i].name, trig->name)) {
1317 return adc->cfg->trigs[i].extsel;
1336 struct stm32_adc *adc = iio_priv(indio_dev);
1348 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE;
1351 spin_lock_irqsave(&adc->lock, flags);
1352 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg);
1353 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask);
1354 val |= exten << adc->cfg->regs->exten.shift;
1355 val |= extsel << adc->cfg->regs->extsel.shift;
1356 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val);
1357 spin_unlock_irqrestore(&adc->lock, flags);
1366 struct stm32_adc *adc = iio_priv(indio_dev);
1368 adc->trigger_polarity = type;
1376 struct stm32_adc *adc = iio_priv(indio_dev);
1378 return adc->trigger_polarity;
1408 struct stm32_adc *adc = iio_priv(indio_dev);
1410 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1415 reinit_completion(&adc->completion);
1417 adc->bufi = 0;
1424 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);
1425 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);
1428 val = stm32_adc_readl(adc, regs->sqr[1].reg);
1431 stm32_adc_writel(adc, regs->sqr[1].reg, val);
1434 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);
1437 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask);
1439 stm32_adc_conv_irq_enable(adc);
1441 adc->cfg->start_conv(indio_dev, false);
1444 &adc->completion, STM32_ADC_TIMEOUT);
1450 *res = adc->buffer[0];
1454 adc->cfg->stop_conv(indio_dev);
1456 stm32_adc_conv_irq_disable(adc);
1468 struct stm32_adc *adc = iio_priv(indio_dev);
1483 *val = STM32_ADC_VREFINT_VOLTAGE * adc->vrefint.vrefint_cal / *val;
1490 *val = adc->common->vref_mv * 2;
1493 *val = adc->common->vref_mv;
1513 struct stm32_adc *adc = iio_priv(indio_dev);
1515 adc->cfg->irq_clear(indio_dev, msk);
1521 struct stm32_adc *adc = iio_priv(indio_dev);
1522 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1523 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1532 adc->cfg->stop_conv(indio_dev);
1544 struct stm32_adc *adc = iio_priv(indio_dev);
1545 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1546 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1556 stm32_adc_ovr_irq_disable(adc);
1557 stm32_adc_conv_irq_disable(adc);
1563 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr);
1565 adc->bufi++;
1566 if (adc->bufi >= adc->num_conv) {
1567 stm32_adc_conv_irq_disable(adc);
1571 complete(&adc->completion);
1580 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1584 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1595 struct stm32_adc *adc = iio_priv(indio_dev);
1606 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv);
1614 struct stm32_adc *adc = iio_priv(indio_dev);
1622 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
1661 struct stm32_adc *adc = iio_priv(indio_dev);
1670 stm32_adc_writel(adc, reg, writeval);
1672 *readval = stm32_adc_readl(adc, reg);
1689 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
1694 status = dmaengine_tx_status(adc->dma_chan,
1695 adc->dma_chan->cookie,
1699 unsigned int i = adc->rx_buf_sz - state.residue;
1703 if (i >= adc->bufi)
1704 size = i - adc->bufi;
1706 size = adc->rx_buf_sz + i - adc->bufi;
1717 struct stm32_adc *adc = iio_priv(indio_dev);
1718 int residue = stm32_adc_dma_residue(adc);
1729 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
1732 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
1737 adc->bufi += indio_dev->scan_bytes;
1738 if (adc->bufi >= adc->rx_buf_sz)
1739 adc->bufi = 0;
1745 struct stm32_adc *adc = iio_priv(indio_dev);
1750 if (!adc->dma_chan)
1754 adc->rx_buf_sz, adc->rx_buf_sz / 2);
1757 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
1758 adc->rx_dma_buf,
1759 adc->rx_buf_sz, adc->rx_buf_sz / 2,
1771 dmaengine_terminate_sync(adc->dma_chan);
1776 dma_async_issue_pending(adc->dma_chan);
1783 struct stm32_adc *adc = iio_priv(indio_dev);
1803 /* Reset adc buffer index */
1804 adc->bufi = 0;
1806 stm32_adc_ovr_irq_enable(adc);
1808 if (!adc->dma_chan)
1809 stm32_adc_conv_irq_enable(adc);
1811 adc->cfg->start_conv(indio_dev, !!adc->dma_chan);
1826 struct stm32_adc *adc = iio_priv(indio_dev);
1829 adc->cfg->stop_conv(indio_dev);
1830 if (!adc->dma_chan)
1831 stm32_adc_conv_irq_disable(adc);
1833 stm32_adc_ovr_irq_disable(adc);
1835 if (adc->dma_chan)
1836 dmaengine_terminate_sync(adc->dma_chan);
1856 struct stm32_adc *adc = iio_priv(indio_dev);
1858 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
1861 adc->bufi = 0;
1862 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
1867 stm32_adc_conv_irq_enable(adc);
1885 struct stm32_adc *adc = iio_priv(indio_dev);
1887 struct stm32_adc_calib *cal = &adc->cal;
1891 if (!adc->cfg->has_linearcal)
1903 struct stm32_adc *adc = iio_priv(indio_dev);
1908 res = adc->cfg->adc_info->resolutions[0];
1910 for (i = 0; i < adc->cfg->adc_info->num_res; i++)
1911 if (res == adc->cfg->adc_info->resolutions[i])
1913 if (i >= adc->cfg->adc_info->num_res) {
1919 adc->res = i;
1924 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns)
1926 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
1935 if (channel == adc->int_ch[i] && adc->int_ch[i] != STM32_ADC_INT_CH_NONE)
1936 smp_ns = max(smp_ns, adc->cfg->ts_int_ch[i]);
1939 period_ns = NSEC_PER_SEC / adc->common->rate;
1941 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns)
1947 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift);
1954 struct stm32_adc *adc = iio_priv(indio_dev);
1955 char *name = adc->chan_name[vinp];
1969 if (chan->channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT])
1976 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];
1981 adc->pcsel |= BIT(chan->channel);
1984 adc->difsel |= BIT(chan->channel) & adc->cfg->regs->difsel.mask;
1986 adc->pcsel |= BIT(chan->channel2);
1990 static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc)
1993 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1998 ret = device_property_count_u32(dev, "st,adc-channels");
2000 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
2007 * each st,adc-diff-channels is a group of 2 u32 so we divide @ret
2010 ret = device_property_count_u32(dev, "st,adc-diff-channels");
2014 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n");
2017 adc->num_diff = ret;
2023 adc->nsmps = device_property_count_u32(dev, "st,min-sample-time-nsecs");
2024 if (adc->nsmps > 1 && adc->nsmps != num_channels) {
2033 struct stm32_adc *adc,
2037 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
2040 u32 num_diff = adc->num_diff;
2047 ret = device_property_read_u32_array(dev, "st,adc-diff-channels",
2069 ret = device_property_read_u32_array(dev, "st,adc-channels", chans, num_se);
2071 dev_err(&indio_dev->dev, "Failed to get st,adc-channels %d\n", ret);
2096 if (adc->nsmps > 0) {
2098 smps, adc->nsmps);
2111 if (i < adc->nsmps)
2115 stm32_adc_smpr_init(adc, channels[i].channel, smp);
2124 struct stm32_adc *adc = iio_priv(indio_dev);
2133 if (!adc->cfg->regs->or_vddcore.reg)
2138 if (!adc->cfg->regs->or_vddcpu.reg)
2143 if (!adc->cfg->regs->or_vddq_ddr.reg)
2148 if (!adc->cfg->regs->ccr_vref.reg)
2153 if (!adc->cfg->regs->ccr_vbat.reg)
2160 adc->int_ch[i] = chan;
2177 adc->int_ch[i] = chan;
2178 adc->vrefint.vrefint_cal = vrefint;
2186 struct stm32_adc *adc,
2189 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
2212 strncpy(adc->chan_name[val], name, STM32_ADC_CH_SZ);
2256 stm32_adc_smpr_init(adc, channels[scan_index].channel, val);
2258 stm32_adc_smpr_init(adc, vin[1], val);
2273 struct stm32_adc *adc = iio_priv(indio_dev);
2274 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
2280 adc->int_ch[i] = STM32_ADC_INT_CH_NONE;
2287 ret = stm32_adc_get_legacy_chan_count(indio_dev, adc);
2313 ret = stm32_adc_legacy_chan_init(indio_dev, adc, channels,
2316 ret = stm32_adc_generic_chan_init(indio_dev, adc, channels);
2342 struct stm32_adc *adc = iio_priv(indio_dev);
2346 adc->dma_chan = dma_request_chan(dev, "rx");
2347 if (IS_ERR(adc->dma_chan)) {
2348 ret = PTR_ERR(adc->dma_chan);
2354 adc->dma_chan = NULL;
2358 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
2360 &adc->rx_dma_buf, GFP_KERNEL);
2361 if (!adc->rx_buf) {
2368 config.src_addr = (dma_addr_t)adc->common->phys_base;
2369 config.src_addr += adc->offset + adc->cfg->regs->dr;
2372 ret = dmaengine_slave_config(adc->dma_chan, &config);
2379 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE,
2380 adc->rx_buf, adc->rx_dma_buf);
2382 dma_release_channel(adc->dma_chan);
2392 struct stm32_adc *adc;
2396 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
2400 adc = iio_priv(indio_dev);
2401 adc->common = dev_get_drvdata(pdev->dev.parent);
2402 spin_lock_init(&adc->lock);
2403 init_completion(&adc->completion);
2404 adc->cfg = device_get_match_data(dev);
2413 ret = device_property_read_u32(dev, "reg", &adc->offset);
2419 adc->irq = platform_get_irq(pdev, 0);
2420 if (adc->irq < 0)
2421 return adc->irq;
2423 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr,
2431 adc->clk = devm_clk_get(&pdev->dev, NULL);
2432 if (IS_ERR(adc->clk)) {
2433 ret = PTR_ERR(adc->clk);
2434 if (ret == -ENOENT && !adc->cfg->clk_required) {
2435 adc->clk = NULL;
2450 if (!adc->dma_chan) {
2471 /* Get stm32-adc-core PM online */
2506 if (adc->dma_chan) {
2507 dma_free_coherent(adc->dma_chan->device->dev,
2509 adc->rx_buf, adc->rx_dma_buf);
2510 dma_release_channel(adc->dma_chan);
2519 struct stm32_adc *adc = iio_priv(indio_dev);
2529 if (adc->dma_chan) {
2530 dma_free_coherent(adc->dma_chan->device->dev,
2532 adc->rx_buf, adc->rx_dma_buf);
2533 dma_release_channel(adc->dma_chan);
2652 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
2653 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
2654 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
2655 { .compatible = "st,stm32mp13-adc", .data = (void *)&stm32mp13_adc_cfg },
2664 .name = "stm32-adc",
2674 MODULE_ALIAS("platform:stm32-adc");