Lines Matching defs:adc
10 #include <linux/iio/adc/qcom-vadc-common.h>
158 static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len)
160 return regmap_bulk_read(adc->regmap, adc->base + offset, data, len);
163 static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len)
165 return regmap_bulk_write(adc->regmap, adc->base + offset, data, len);
168 static int adc5_masked_write(struct adc5_chip *adc, u16 offset, u8 mask, u8 val)
170 return regmap_update_bits(adc->regmap, adc->base + offset, mask, val);
173 static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data)
178 ret = adc5_read(adc, ADC5_USR_DATA0, &rslt_lsb, sizeof(rslt_lsb));
182 ret = adc5_read(adc, ADC5_USR_DATA1, &rslt_msb, sizeof(rslt_lsb));
189 dev_err(adc->dev, "Invalid data:0x%x\n", *data);
193 dev_dbg(adc->dev, "voltage raw code:0x%x\n", *data);
198 static int adc5_poll_wait_eoc(struct adc5_chip *adc)
205 ret = adc5_read(adc, ADC5_USR_STATUS1, &status1,
220 static void adc5_update_dig_param(struct adc5_chip *adc,
236 static int adc5_configure(struct adc5_chip *adc,
243 ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
248 adc5_update_dig_param(adc, prop, &buf[0]);
267 if (!adc->poll_eoc)
268 reinit_completion(&adc->complete);
270 return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
273 static int adc7_configure(struct adc5_chip *adc,
279 ret = adc5_masked_write(adc, ADC_APP_SID, ADC_APP_SID_MASK, prop->sid);
283 ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
288 adc5_update_dig_param(adc, prop, &buf[0]);
304 if (!adc->poll_eoc)
305 reinit_completion(&adc->complete);
307 ret = adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
311 return adc5_write(adc, ADC5_USR_CONV_REQ, &conv_req, 1);
314 static int adc5_do_conversion(struct adc5_chip *adc,
321 mutex_lock(&adc->lock);
323 ret = adc5_configure(adc, prop);
325 dev_err(adc->dev, "ADC configure failed with %d\n", ret);
329 if (adc->poll_eoc) {
330 ret = adc5_poll_wait_eoc(adc);
332 dev_err(adc->dev, "EOC bit not set\n");
336 ret = wait_for_completion_timeout(&adc->complete,
339 dev_dbg(adc->dev, "Did not get completion timeout.\n");
340 ret = adc5_poll_wait_eoc(adc);
342 dev_err(adc->dev, "EOC bit not set\n");
348 ret = adc5_read_voltage_data(adc, data_volt);
350 mutex_unlock(&adc->lock);
355 static int adc7_do_conversion(struct adc5_chip *adc,
363 mutex_lock(&adc->lock);
365 ret = adc7_configure(adc, prop);
367 dev_err(adc->dev, "ADC configure failed with %d\n", ret);
372 wait_for_completion_timeout(&adc->complete, ADC7_CONV_TIMEOUT);
374 ret = adc5_read(adc, ADC5_USR_STATUS1, &status, 1);
379 dev_err(adc->dev, "Unexpected conversion fault\n");
384 ret = adc5_read_voltage_data(adc, data_volt);
387 mutex_unlock(&adc->lock);
392 typedef int (*adc_do_conversion)(struct adc5_chip *adc,
399 struct adc5_chip *adc = dev_id;
401 complete(&adc->complete);
409 struct adc5_chip *adc = iio_priv(indio_dev);
412 for (i = 0; i < adc->nchannels; i++)
413 if (adc->chan_props[i].channel == iiospec->args[0])
422 struct adc5_chip *adc = iio_priv(indio_dev);
425 for (i = 0; i < adc->nchannels; i++) {
426 v_channel = (adc->chan_props[i].sid << ADC_CHANNEL_OFFSET) |
427 adc->chan_props[i].channel;
439 struct adc5_chip *adc = iio_priv(indio_dev);
444 prop = &adc->chan_props[chan->address];
448 ret = do_conv(adc, prop, chan,
455 adc->data,
628 static int adc5_get_fw_channel_data(struct adc5_chip *adc,
638 struct device *dev = adc->dev;
657 if (adc->data->info == &adc7_info) {
701 adc->data->adc_chans[prop->channel].prescale_index;
708 ret = adc5_read(adc, ADC5_USR_REVISION1, dig_version,
720 adc->data->info == &adc7_info)
816 .compatible = "qcom,spmi-adc-rev2",
823 static int adc5_get_fw_data(struct adc5_chip *adc)
832 adc->nchannels = device_get_child_node_count(adc->dev);
833 if (!adc->nchannels)
836 adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
837 sizeof(*adc->iio_chans), GFP_KERNEL);
838 if (!adc->iio_chans)
841 adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
842 sizeof(*adc->chan_props), GFP_KERNEL);
843 if (!adc->chan_props)
846 chan_props = adc->chan_props;
847 iio_chan = adc->iio_chans;
848 adc->data = device_get_match_data(adc->dev);
849 if (!adc->data)
850 adc->data = &adc5_data_pmic;
852 device_for_each_child_node(adc->dev, child) {
853 ret = adc5_get_fw_channel_data(adc, &prop, child, adc->data);
860 adc->data->adc_chans[prop.channel].scale_fn_type;
862 adc_chan = &adc->data->adc_chans[prop.channel];
882 struct adc5_chip *adc;
895 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
899 adc = iio_priv(indio_dev);
900 adc->regmap = regmap;
901 adc->dev = dev;
902 adc->base = reg;
904 init_completion(&adc->complete);
905 mutex_init(&adc->lock);
907 ret = adc5_get_fw_data(adc);
909 return dev_err_probe(dev, ret, "adc get dt data failed\n");
915 adc->poll_eoc = true;
918 "pm-adc5", adc);
925 indio_dev->info = adc->data->info;
926 indio_dev->channels = adc->iio_chans;
927 indio_dev->num_channels = adc->nchannels;