Lines Matching defs:adc
3 * palmas-adc.c -- TI PALMAS GPADC.
131 static struct palmas_adc_event *palmas_gpadc_get_event(struct palmas_gpadc *adc,
135 if (adc_chan == adc->event0.channel && dir == adc->event0.direction)
136 return &adc->event0;
138 if (adc_chan == adc->event1.channel && dir == adc->event1.direction)
139 return &adc->event1;
144 static bool palmas_gpadc_channel_is_freerunning(struct palmas_gpadc *adc,
147 return palmas_gpadc_get_event(adc, adc_chan, IIO_EV_DIR_RISING) ||
148 palmas_gpadc_get_event(adc, adc_chan, IIO_EV_DIR_FALLING);
175 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc)
179 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
184 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
188 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
194 dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret);
200 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
204 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
211 struct palmas_gpadc *adc = data;
213 complete(&adc->conv_completion);
221 struct palmas_gpadc *adc = iio_priv(indio_dev);
224 dev_dbg(adc->dev, "Threshold interrupt %d occurs\n", irq);
225 palmas_disable_auto_conversion(adc);
227 ev = (irq == adc->irq_auto_0) ? &adc->event0 : &adc->event1;
241 static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc,
247 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
251 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
256 dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret);
261 static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan,
268 val = (adc->extended_delay
270 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
274 dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret);
281 val = (adc->ch0_current
283 val |= (adc->ch3_current
286 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
289 dev_err(adc->dev,
297 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
300 dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret);
304 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
307 dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret);
309 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
313 dev_err(adc->dev, "CTRL1 update failed: %d\n", ret);
321 static int palmas_gpadc_read_prepare(struct palmas_gpadc *adc, int adc_chan)
325 if (palmas_gpadc_channel_is_freerunning(adc, adc_chan))
328 ret = palmas_gpadc_enable(adc, adc_chan, true);
332 return palmas_gpadc_start_mask_interrupt(adc, 0);
335 static void palmas_gpadc_read_done(struct palmas_gpadc *adc, int adc_chan)
337 palmas_gpadc_start_mask_interrupt(adc, 1);
338 palmas_gpadc_enable(adc, adc_chan, false);
341 static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan)
348 int x1 = adc->adc_info[adc_chan].x1;
349 int x2 = adc->adc_info[adc_chan].x2;
350 int v1 = adc->adc_info[adc_chan].v1;
351 int v2 = adc->adc_info[adc_chan].v2;
353 ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
354 adc->adc_info[adc_chan].trim1_reg, &d1);
356 dev_err(adc->dev, "TRIM read failed: %d\n", ret);
360 ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
361 adc->adc_info[adc_chan].trim2_reg, &d2);
363 dev_err(adc->dev, "TRIM read failed: %d\n", ret);
373 adc->adc_info[adc_chan].gain_error = k;
374 adc->adc_info[adc_chan].gain = gain;
376 adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1);
382 static int palmas_gpadc_start_conversion(struct palmas_gpadc *adc, int adc_chan)
387 if (palmas_gpadc_channel_is_freerunning(adc, adc_chan)) {
388 int event = (adc_chan == adc->event0.channel) ? 0 : 1;
393 ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE,
396 dev_err(adc->dev, "AUTO_CONV%x_LSB read failed: %d\n",
401 init_completion(&adc->conv_completion);
402 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
407 dev_err(adc->dev, "SELECT_SW_START write failed: %d\n", ret);
411 ret = wait_for_completion_timeout(&adc->conv_completion,
414 dev_err(adc->dev, "conversion not completed\n");
418 ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE,
421 dev_err(adc->dev, "SW_CONV0_LSB read failed: %d\n", ret);
431 static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc,
434 if (!adc->adc_info[adc_chan].is_uncalibrated)
435 val = (val*1000 - adc->adc_info[adc_chan].offset) /
436 adc->adc_info[adc_chan].gain_error;
440 dev_err(adc->dev, "Mismatch with calibration var = %d\n", val);
444 val = (val * adc->adc_info[adc_chan].gain) / 1000;
475 static int palmas_gpadc_get_high_threshold_raw(struct palmas_gpadc *adc,
479 int val = adc->thresholds[adc_chan].high;
487 val = (val * 1000) / adc->adc_info[adc_chan].gain;
489 if (adc->adc_info[adc_chan].is_uncalibrated) {
494 val = (val * adc->adc_info[adc_chan].gain_error +
495 adc->adc_info[adc_chan].offset) /
510 static int palmas_gpadc_get_low_threshold_raw(struct palmas_gpadc *adc,
514 int val = adc->thresholds[adc_chan].low;
522 val = (val * 1000) / adc->adc_info[adc_chan].gain;
524 if (adc->adc_info[adc_chan].is_uncalibrated) {
529 val = (val * adc->adc_info[adc_chan].gain_error -
530 adc->adc_info[adc_chan].offset) /
544 struct palmas_gpadc *adc = iio_priv(indio_dev);
551 mutex_lock(&adc->lock);
556 ret = palmas_gpadc_read_prepare(adc, adc_chan);
560 ret = palmas_gpadc_start_conversion(adc, adc_chan);
562 dev_err(adc->dev,
569 adc, adc_chan, ret);
577 mutex_unlock(&adc->lock);
581 palmas_gpadc_read_done(adc, adc_chan);
582 mutex_unlock(&adc->lock);
592 struct palmas_gpadc *adc = iio_priv(indio_dev);
599 mutex_lock(&adc->lock);
601 if (palmas_gpadc_get_event(adc, adc_chan, dir))
604 mutex_unlock(&adc->lock);
609 static int palmas_adc_configure_events(struct palmas_gpadc *adc);
610 static int palmas_adc_reset_events(struct palmas_gpadc *adc);
612 static int palmas_gpadc_reconfigure_event_channels(struct palmas_gpadc *adc)
614 return (adc->event0.enabled || adc->event1.enabled) ?
615 palmas_adc_configure_events(adc) :
616 palmas_adc_reset_events(adc);
619 static int palmas_gpadc_enable_event_config(struct palmas_gpadc *adc,
626 if (palmas_gpadc_get_event(adc, adc_chan, dir))
630 if (adc->event0.channel == -1) {
631 ev = &adc->event0;
632 } else if (adc->event1.channel == -1) {
634 if (adc_chan < adc->event0.channel) {
635 adc->event1 = adc->event0;
636 ev = &adc->event0;
638 ev = &adc->event1;
641 dev_warn(adc->dev, "event0 - %d, event1 - %d\n",
642 adc->event0.channel, adc->event1.channel);
650 return palmas_gpadc_reconfigure_event_channels(adc);
653 static int palmas_gpadc_disable_event_config(struct palmas_gpadc *adc,
658 struct palmas_adc_event *ev = palmas_gpadc_get_event(adc, adc_chan, dir);
663 if (ev == &adc->event0) {
664 adc->event0 = adc->event1;
665 ev = &adc->event1;
672 return palmas_gpadc_reconfigure_event_channels(adc);
681 struct palmas_gpadc *adc = iio_priv(indio_dev);
688 mutex_lock(&adc->lock);
691 ret = palmas_gpadc_enable_event_config(adc, chan, dir);
693 ret = palmas_gpadc_disable_event_config(adc, chan, dir);
695 mutex_unlock(&adc->lock);
707 struct palmas_gpadc *adc = iio_priv(indio_dev);
714 mutex_lock(&adc->lock);
719 adc->thresholds[adc_chan].high :
720 adc->thresholds[adc_chan].low;
728 mutex_unlock(&adc->lock);
740 struct palmas_gpadc *adc = iio_priv(indio_dev);
748 mutex_lock(&adc->lock);
756 old = adc->thresholds[adc_chan].high;
757 adc->thresholds[adc_chan].high = val;
759 old = adc->thresholds[adc_chan].low;
760 adc->thresholds[adc_chan].low = val;
769 if (val != old && palmas_gpadc_get_event(adc, adc_chan, dir))
770 ret = palmas_gpadc_reconfigure_event_channels(adc);
773 mutex_unlock(&adc->lock);
861 struct palmas_gpadc *adc = data;
862 if (adc->event0.enabled || adc->event1.enabled)
863 palmas_adc_reset_events(adc);
868 struct palmas_gpadc *adc;
887 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
893 adc = iio_priv(indio_dev);
894 adc->dev = &pdev->dev;
895 adc->palmas = dev_get_drvdata(pdev->dev.parent);
896 adc->adc_info = palmas_gpadc_info;
898 mutex_init(&adc->lock);
900 init_completion(&adc->conv_completion);
903 adc->auto_conversion_period = gpadc_pdata->auto_conversion_period_ms;
904 adc->irq = palmas_irq_get_virq(adc->palmas, PALMAS_GPADC_EOC_SW_IRQ);
905 if (adc->irq < 0)
906 return dev_err_probe(adc->dev, adc->irq, "get virq failed\n");
908 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, NULL,
910 IRQF_ONESHOT, dev_name(adc->dev),
911 adc);
913 return dev_err_probe(adc->dev, ret,
914 "request irq %d failed\n", adc->irq);
916 adc->irq_auto_0 = platform_get_irq(pdev, 1);
917 if (adc->irq_auto_0 < 0)
918 return adc->irq_auto_0;
920 ret = devm_request_threaded_irq(&pdev->dev, adc->irq_auto_0, NULL,
922 "palmas-adc-auto-0", indio_dev);
924 return dev_err_probe(adc->dev, ret,
926 adc->irq_auto_0);
928 adc->irq_auto_1 = platform_get_irq(pdev, 2);
929 if (adc->irq_auto_1 < 0)
930 return adc->irq_auto_1;
932 ret = devm_request_threaded_irq(&pdev->dev, adc->irq_auto_1, NULL,
934 "palmas-adc-auto-1", indio_dev);
936 return dev_err_probe(adc->dev, ret,
938 adc->irq_auto_1);
940 adc->event0.enabled = false;
941 adc->event0.channel = -1;
942 adc->event0.direction = IIO_EV_DIR_NONE;
943 adc->event1.enabled = false;
944 adc->event1.channel = -1;
945 adc->event1.direction = IIO_EV_DIR_NONE;
949 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0;
951 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5;
953 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15;
955 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20;
959 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0;
961 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10;
963 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400;
965 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800;
967 adc->extended_delay = gpadc_pdata->extended_delay;
977 return dev_err_probe(adc->dev, ret,
982 if (!(adc->adc_info[i].is_uncalibrated))
983 palmas_gpadc_calibrate(adc, i);
986 ret = devm_add_action(&pdev->dev, palmas_gpadc_reset, adc);
993 static int palmas_adc_configure_events(struct palmas_gpadc *adc)
1001 adc_period = adc->auto_conversion_period;
1009 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
1014 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
1019 if (adc->event0.enabled) {
1020 struct palmas_adc_event *ev = &adc->event0;
1027 thres = palmas_gpadc_get_high_threshold_raw(adc, ev);
1031 thres = palmas_gpadc_get_low_threshold_raw(adc, ev);
1038 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
1041 dev_err(adc->dev,
1046 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
1050 dev_err(adc->dev,
1056 if (adc->event1.enabled) {
1057 struct palmas_adc_event *ev = &adc->event1;
1064 thres = palmas_gpadc_get_high_threshold_raw(adc, ev);
1068 thres = palmas_gpadc_get_low_threshold_raw(adc, ev);
1075 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
1078 dev_err(adc->dev,
1083 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
1087 dev_err(adc->dev,
1093 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
1096 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
1100 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
1105 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
1110 static int palmas_adc_reset_events(struct palmas_gpadc *adc)
1114 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
1117 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
1121 ret = palmas_disable_auto_conversion(adc);
1123 dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret);
1131 struct palmas_gpadc *adc = iio_priv(indio_dev);
1136 if (adc->event0.enabled)
1137 enable_irq_wake(adc->irq_auto_0);
1139 if (adc->event1.enabled)
1140 enable_irq_wake(adc->irq_auto_1);
1148 struct palmas_gpadc *adc = iio_priv(indio_dev);
1153 if (adc->event0.enabled)
1154 disable_irq_wake(adc->irq_auto_0);
1156 if (adc->event1.enabled)
1157 disable_irq_wake(adc->irq_auto_1);