Lines Matching defs:channel
116 u32 channel;
147 .channel = (_idx), \
195 * Before sample set, disable channel A,B,C,D. Here we
225 /* enable channel A,B,C,D interrupt */
238 u32 channel;
240 channel = info->channel;
242 /* the channel choose single conversion, and enable average mode */
248 * physical channel 0 chose logical channel A
249 * physical channel 1 chose logical channel B
250 * physical channel 2 chose logical channel C
251 * physical channel 3 chose logical channel D
253 cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(channel);
257 * channel chosen
259 cfg2 = readl(info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
266 * the channel chosen
268 writel(cfg2, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
270 writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel);
293 u32 channel;
301 channel = chan->channel & 0x03;
302 info->channel = channel;
337 u32 channel;
340 channel = info->channel & 0x03;
343 * channel A and B conversion result share one register,
344 * bit[27~16] is the channel B conversion result,
345 * bit[11~0] is the channel A conversion result.
346 * channel C and D is the same.
348 if (channel < 2)
352 if (channel & 0x1) /* channel B or D */
354 else /* channel A or C */
373 * 0 to the related bit. Here we clear the channel A/B/C/D
381 * If the channel A/B/C/D conversion timeout, report it and clear these