Lines Matching refs:st
428 #define at91_adc_readl(st, reg) \
429 readl_relaxed((st)->base + (st)->soc_info.platform->layout->reg)
430 #define at91_adc_read_chan(st, reg) \
431 readl_relaxed((st)->base + reg)
432 #define at91_adc_writel(st, reg, val) \
433 writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg)
777 struct at91_adc_state *st = iio_priv(indio_dev);
786 return mask & GENMASK(st->soc_info.platform->nr_channels, 0);
789 static void at91_adc_cor(struct at91_adc_state *st,
796 cur_cor = at91_adc_readl(st, COR);
797 cor <<= st->soc_info.platform->layout->COR_diff_offset;
799 at91_adc_writel(st, COR, cur_cor | cor);
801 at91_adc_writel(st, COR, cur_cor & ~cor);
804 static void at91_adc_irq_status(struct at91_adc_state *st, u32 *status,
807 *status = at91_adc_readl(st, ISR);
808 if (st->soc_info.platform->layout->EOC_ISR)
809 *eoc = at91_adc_readl(st, EOC_ISR);
814 static void at91_adc_irq_mask(struct at91_adc_state *st, u32 *status, u32 *eoc)
816 *status = at91_adc_readl(st, IMR);
817 if (st->soc_info.platform->layout->EOC_IMR)
818 *eoc = at91_adc_readl(st, EOC_IMR);
823 static void at91_adc_eoc_dis(struct at91_adc_state *st, unsigned int channel)
830 if (!st->soc_info.platform->layout->EOC_IDR)
831 at91_adc_writel(st, IDR, BIT(channel));
834 static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel)
836 if (!st->soc_info.platform->layout->EOC_IDR)
837 at91_adc_writel(st, IER, BIT(channel));
839 at91_adc_writel(st, EOC_IER, BIT(channel));
842 static int at91_adc_config_emr(struct at91_adc_state *st,
847 unsigned int osr_mask = st->soc_info.platform->osr_mask;
851 for (i = 0; i < st->soc_info.platform->oversampling_avail_no; i++) {
852 if (oversampling_ratio == st->soc_info.platform->oversampling_avail[i])
855 if (i == st->soc_info.platform->oversampling_avail_no)
882 ret = pm_runtime_resume_and_get(st->dev);
886 emr = at91_adc_readl(st, EMR);
893 at91_adc_writel(st, EMR, emr);
895 pm_runtime_mark_last_busy(st->dev);
896 pm_runtime_put_autosuspend(st->dev);
898 st->oversampling_ratio = oversampling_ratio;
903 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
907 if (st->oversampling_ratio == 1)
909 else if (st->oversampling_ratio == 4)
911 else if (st->oversampling_ratio == 16)
913 else if (st->oversampling_ratio == 64)
915 else if (st->oversampling_ratio == 256)
923 * st->soc_info.platform->chan_realbits, so shift left diff bits.
925 diff = st->soc_info.platform->chan_realbits - nbits;
931 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf,
947 at91_adc_adjust_val_osr(st, &val);
953 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state)
955 u32 clk_khz = st->current_sample_rate / 1000;
961 ret = pm_runtime_resume_and_get(st->dev);
966 at91_adc_writel(st, IDR,
968 at91_adc_writel(st, TSMR, 0);
970 pm_runtime_mark_last_busy(st->dev);
971 pm_runtime_put_autosuspend(st->dev);
997 at91_adc_writel(st, TSMR, tsmr);
999 acr = at91_adc_readl(st, ACR);
1002 at91_adc_writel(st, ACR, acr);
1005 st->touch_st.sample_period_val =
1009 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);
1014 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg)
1025 if (reg == st->soc_info.platform->layout->XPOSR)
1026 val = at91_adc_readl(st, XPOSR);
1027 else if (reg == st->soc_info.platform->layout->YPOSR)
1028 val = at91_adc_readl(st, YPOSR);
1031 dev_dbg(&st->indio_dev->dev, "pos is 0\n");
1037 dev_err(&st->indio_dev->dev, "scale is 0\n");
1045 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st)
1047 st->touch_st.x_pos = at91_adc_touch_pos(st, st->soc_info.platform->layout->XPOSR);
1048 return st->touch_st.x_pos;
1051 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st)
1053 return at91_adc_touch_pos(st, st->soc_info.platform->layout->YPOSR);
1056 static u16 at91_adc_touch_pressure(struct at91_adc_state *st)
1065 val = at91_adc_readl(st, PRESSR);
1070 pres = rxp * (st->touch_st.x_pos * factor / 1024) *
1084 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val)
1087 if (!st->touch_st.touching)
1089 if (chan == st->soc_info.platform->touch_chan_x)
1090 *val = at91_adc_touch_x_pos(st);
1091 else if (chan == st->soc_info.platform->touch_chan_y)
1092 *val = at91_adc_touch_y_pos(st);
1099 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val)
1102 if (!st->touch_st.touching)
1104 if (chan == st->soc_info.platform->touch_chan_p)
1105 *val = at91_adc_touch_pressure(st);
1112 static void at91_adc_configure_trigger_registers(struct at91_adc_state *st,
1115 u32 status = at91_adc_readl(st, TRGR);
1121 status |= st->selected_trig->trgmod_value;
1124 at91_adc_writel(st, TRGR, status);
1130 struct at91_adc_state *st = iio_priv(indio);
1134 ret = pm_runtime_resume_and_get(st->dev);
1139 at91_adc_configure_trigger_registers(st, state);
1142 pm_runtime_mark_last_busy(st->dev);
1143 pm_runtime_put_autosuspend(st->dev);
1152 struct at91_adc_state *st = iio_priv(indio);
1155 if (st->dma_st.dma_chan)
1158 enable_irq(st->irq);
1161 at91_adc_readl(st, LCDR);
1170 static int at91_adc_dma_size_done(struct at91_adc_state *st)
1176 status = dmaengine_tx_status(st->dma_st.dma_chan,
1177 st->dma_st.dma_chan->cookie,
1183 i = st->dma_st.rx_buf_sz - state.residue;
1186 if (i >= st->dma_st.buf_idx)
1187 size = i - st->dma_st.buf_idx;
1189 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx;
1202 struct at91_adc_state *st = iio_priv(indio_dev);
1208 if (!st->dma_st.dma_chan)
1212 st->dma_st.buf_idx = 0;
1218 st->dma_st.rx_buf_sz = 0;
1228 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8;
1230 st->dma_st.rx_buf_sz *= st->dma_st.watermark;
1233 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan,
1234 st->dma_st.rx_dma_buf,
1235 st->dma_st.rx_buf_sz,
1236 st->dma_st.rx_buf_sz / 2,
1251 dmaengine_terminate_async(st->dma_st.dma_chan);
1256 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_GOVRE);
1258 dma_async_issue_pending(st->dma_st.dma_chan);
1261 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1269 struct at91_adc_state *st)
1272 if (st->dma_st.dma_chan)
1282 struct at91_adc_state *st = iio_priv(indio_dev);
1285 &st->touch_st.channels_bitmask,
1286 st->soc_info.platform->max_index + 1);
1293 struct at91_adc_state *st = iio_priv(indio_dev);
1297 return at91_adc_configure_touch(st, true);
1303 ret = pm_runtime_resume_and_get(st->dev);
1326 at91_adc_cor(st, chan);
1328 at91_adc_writel(st, CHER, BIT(chan->channel));
1331 if (at91_adc_buffer_check_use_irq(indio_dev, st))
1332 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_DRDY);
1335 pm_runtime_mark_last_busy(st->dev);
1336 pm_runtime_put_autosuspend(st->dev);
1342 struct at91_adc_state *st = iio_priv(indio_dev);
1348 return at91_adc_configure_touch(st, false);
1354 ret = pm_runtime_resume_and_get(st->dev);
1377 at91_adc_writel(st, CHDR, BIT(chan->channel));
1379 if (st->dma_st.dma_chan)
1380 at91_adc_read_chan(st, chan->address);
1383 if (at91_adc_buffer_check_use_irq(indio_dev, st))
1384 at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_DRDY);
1387 at91_adc_readl(st, OVER);
1390 if (st->dma_st.dma_chan)
1391 dmaengine_terminate_sync(st->dma_st.dma_chan);
1393 pm_runtime_mark_last_busy(st->dev);
1394 pm_runtime_put_autosuspend(st->dev);
1428 struct at91_adc_state *st = iio_priv(indio_dev);
1441 at91_adc_irq_status(st, &status, &eoc);
1442 at91_adc_irq_mask(st, &imr, &eoc_imr);
1469 val = at91_adc_read_chan(st, chan->address);
1470 at91_adc_adjust_val_osr(st, &val);
1471 st->buffer[i] = val;
1473 st->buffer[i] = 0;
1478 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer,
1484 struct at91_adc_state *st = iio_priv(indio_dev);
1485 int transferred_len = at91_adc_dma_size_done(st);
1490 u32 status = at91_adc_readl(st, ISR);
1496 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark);
1504 interval = div_s64((ns - st->dma_st.dma_ts), sample_count);
1511 at91_adc_adjust_val_osr_array(st,
1512 &st->dma_st.rx_buf[st->dma_st.buf_idx],
1516 (st->dma_st.rx_buf + st->dma_st.buf_idx),
1517 (st->dma_st.dma_ts + interval * sample_index));
1521 st->dma_st.buf_idx += sample_size;
1523 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz)
1524 st->dma_st.buf_idx = 0;
1528 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1535 struct at91_adc_state *st = iio_priv(indio_dev);
1542 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START);
1544 if (st->dma_st.dma_chan)
1582 struct at91_adc_state *st = iio_priv(indio_dev);
1586 f_per = clk_get_rate(st->per_clk);
1591 ret = pm_runtime_resume_and_get(st->dev);
1595 mr = at91_adc_readl(st, MR);
1600 at91_adc_writel(st, MR, mr);
1602 pm_runtime_mark_last_busy(st->dev);
1603 pm_runtime_put_autosuspend(st->dev);
1607 st->current_sample_rate = freq;
1610 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
1612 return st->current_sample_rate;
1617 struct at91_adc_state *st = iio_priv(indio_dev);
1623 st->soc_info.platform->max_index + 1) {
1628 at91_adc_read_position(st, chan->channel, &val);
1630 at91_adc_read_pressure(st, chan->channel, &val);
1633 st->buffer[i] = val;
1644 schedule_work(&st->touch_st.workq);
1647 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st)
1649 at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_PEN);
1650 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_NOPEN |
1653 at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |
1654 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val));
1655 st->touch_st.touching = true;
1660 struct at91_adc_state *st = iio_priv(indio_dev);
1662 at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);
1663 at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_NOPEN |
1666 st->touch_st.touching = false;
1670 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);
1677 struct at91_adc_state *st = container_of(touch_st,
1679 struct iio_dev *indio_dev = st->indio_dev;
1681 iio_push_to_buffers(indio_dev, st->buffer);
1687 struct at91_adc_state *st = iio_priv(indio);
1692 at91_adc_irq_status(st, &status, &eoc);
1693 at91_adc_irq_mask(st, &imr, &eoc_imr);
1699 at91_adc_pen_detect_interrupt(st);
1712 status = at91_adc_readl(st, XPOSR);
1713 status = at91_adc_readl(st, YPOSR);
1714 status = at91_adc_readl(st, PRESSR);
1720 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) {
1726 st->conversion_value = at91_adc_read_chan(st, st->chan->address);
1727 st->conversion_done = true;
1728 wake_up_interruptible(&st->wq_data_available);
1733 /* This needs to be called with direct mode claimed and st->lock locked. */
1737 struct at91_adc_state *st = iio_priv(indio_dev);
1741 ret = pm_runtime_resume_and_get(st->dev);
1750 ret = at91_adc_read_position(st, chan->channel,
1754 ret = at91_adc_adjust_val_osr(st, val);
1759 ret = at91_adc_read_pressure(st, chan->channel,
1763 ret = at91_adc_adjust_val_osr(st, val);
1770 st->chan = chan;
1772 at91_adc_cor(st, chan);
1773 at91_adc_writel(st, CHER, BIT(chan->channel));
1780 at91_adc_writel(st, TEMPMR, AT91_SAMA5D2_TEMPMR_TEMPON);
1781 at91_adc_eoc_ena(st, chan->channel);
1782 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START);
1784 ret = wait_event_interruptible_timeout(st->wq_data_available,
1785 st->conversion_done,
1791 *val = st->conversion_value;
1792 ret = at91_adc_adjust_val_osr(st, val);
1796 st->conversion_done = false;
1799 at91_adc_eoc_dis(st, st->chan->channel);
1801 at91_adc_writel(st, TEMPMR, 0U);
1802 at91_adc_writel(st, CHDR, BIT(chan->channel));
1805 at91_adc_readl(st, LCDR);
1808 pm_runtime_mark_last_busy(st->dev);
1809 pm_runtime_put_autosuspend(st->dev);
1816 struct at91_adc_state *st = iio_priv(indio_dev);
1823 mutex_lock(&st->lock);
1825 mutex_unlock(&st->lock);
1832 static void at91_adc_temp_sensor_configure(struct at91_adc_state *st,
1849 st->temp_st.saved_sample_rate = st->current_sample_rate;
1850 st->temp_st.saved_oversampling = st->oversampling_ratio;
1853 sample_rate = st->temp_st.saved_sample_rate;
1854 oversampling_ratio = st->temp_st.saved_oversampling;
1855 startup_time = st->soc_info.startup_time;
1860 at91_adc_setup_samp_freq(st->indio_dev, sample_rate, startup_time,
1862 at91_adc_config_emr(st, oversampling_ratio, trackx);
1868 struct at91_adc_state *st = iio_priv(indio_dev);
1869 struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb;
1877 mutex_lock(&st->lock);
1879 ret = pm_runtime_resume_and_get(st->dev);
1883 at91_adc_temp_sensor_configure(st, true);
1886 tmp = at91_adc_readl(st, ACR);
1888 at91_adc_writel(st, ACR, tmp);
1895 at91_adc_writel(st, ACR, tmp);
1900 at91_adc_temp_sensor_configure(st, false);
1901 pm_runtime_mark_last_busy(st->dev);
1902 pm_runtime_put_autosuspend(st->dev);
1904 mutex_unlock(&st->lock);
1926 struct at91_adc_state *st = iio_priv(indio_dev);
1933 *val = st->vref_uv / 1000;
1945 *val = at91_adc_get_sample_freq(st);
1949 *val = st->oversampling_ratio;
1961 struct at91_adc_state *st = iio_priv(indio_dev);
1967 if (val == st->oversampling_ratio)
1973 mutex_lock(&st->lock);
1975 ret = at91_adc_config_emr(st, val, 0);
1976 mutex_unlock(&st->lock);
1980 if (val < st->soc_info.min_sample_rate ||
1981 val > st->soc_info.max_sample_rate)
1987 mutex_lock(&st->lock);
1989 st->soc_info.startup_time, 0);
1990 mutex_unlock(&st->lock);
2003 struct at91_adc_state *st = iio_priv(indio_dev);
2007 *vals = (int *)st->soc_info.platform->oversampling_avail;
2009 *length = st->soc_info.platform->oversampling_avail_no;
2016 static void at91_adc_dma_init(struct at91_adc_state *st)
2018 struct device *dev = &st->indio_dev->dev;
2021 unsigned int sample_size = st->soc_info.platform->nr_channels * 2;
2030 if (st->dma_st.dma_chan)
2033 st->dma_st.dma_chan = dma_request_chan(dev, "rx");
2034 if (IS_ERR(st->dma_st.dma_chan)) {
2036 st->dma_st.dma_chan = NULL;
2040 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev,
2042 &st->dma_st.rx_dma_buf,
2044 if (!st->dma_st.rx_buf) {
2051 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr
2052 + st->soc_info.platform->layout->LCDR);
2057 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) {
2063 dma_chan_name(st->dma_st.dma_chan));
2068 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
2069 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
2071 dma_release_channel(st->dma_st.dma_chan);
2072 st->dma_st.dma_chan = NULL;
2077 static void at91_adc_dma_disable(struct at91_adc_state *st)
2079 struct device *dev = &st->indio_dev->dev;
2081 unsigned int sample_size = st->soc_info.platform->nr_channels * 2;
2086 if (!st->dma_st.dma_chan)
2090 dmaengine_terminate_sync(st->dma_st.dma_chan);
2092 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
2093 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
2094 dma_release_channel(st->dma_st.dma_chan);
2095 st->dma_st.dma_chan = NULL;
2102 struct at91_adc_state *st = iio_priv(indio_dev);
2108 if (!st->selected_trig->hw_trig) {
2114 st->dma_st.watermark = val;
2123 at91_adc_dma_disable(st);
2125 at91_adc_dma_init(st);
2133 at91_adc_dma_disable(st);
2141 struct at91_adc_state *st = iio_priv(indio_dev);
2143 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask,
2144 st->soc_info.platform->max_index + 1))
2150 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask,
2151 st->soc_info.platform->max_index + 1))
2158 struct at91_adc_state *st = iio_priv(indio_dev);
2160 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST);
2161 if (st->soc_info.platform->layout->EOC_IDR)
2162 at91_adc_writel(st, EOC_IDR, 0xffffffff);
2163 at91_adc_writel(st, IDR, 0xffffffff);
2168 at91_adc_writel(st, MR,
2171 at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate,
2172 st->soc_info.startup_time, 0);
2175 at91_adc_config_emr(st, st->oversampling_ratio, 0);
2182 struct at91_adc_state *st = iio_priv(indio_dev);
2184 return sysfs_emit(buf, "%d\n", !!st->dma_st.dma_chan);
2191 struct at91_adc_state *st = iio_priv(indio_dev);
2193 return sysfs_emit(buf, "%d\n", st->dma_st.watermark);
2224 struct at91_adc_state *st = iio_priv(indio);
2228 if (st->selected_trig->hw_trig)
2241 if (!st->selected_trig->hw_trig)
2244 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
2245 if (IS_ERR(st->trig)) {
2247 return PTR_ERR(st->trig);
2254 st->dma_st.watermark = 1;
2259 static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
2262 struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb;
2268 if (!st->soc_info.platform->temp_sensor)
2310 struct at91_adc_state *st;
2315 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
2319 st = iio_priv(indio_dev);
2320 st->indio_dev = indio_dev;
2322 st->soc_info.platform = device_get_match_data(dev);
2324 ret = at91_adc_temp_sensor_init(st, &pdev->dev);
2327 num_channels = st->soc_info.platform->max_channels - 1;
2329 num_channels = st->soc_info.platform->max_channels;
2334 indio_dev->channels = *st->soc_info.platform->adc_channels;
2337 bitmap_set(&st->touch_st.channels_bitmask,
2338 st->soc_info.platform->touch_chan_x, 1);
2339 bitmap_set(&st->touch_st.channels_bitmask,
2340 st->soc_info.platform->touch_chan_y, 1);
2341 bitmap_set(&st->touch_st.channels_bitmask,
2342 st->soc_info.platform->touch_chan_p, 1);
2344 st->oversampling_ratio = 1;
2347 &st->soc_info.min_sample_rate);
2355 &st->soc_info.max_sample_rate);
2363 &st->soc_info.startup_time);
2377 st->selected_trig = NULL;
2380 for (i = 0; i < st->soc_info.platform->hw_trig_cnt + 1; i++)
2382 st->selected_trig = &at91_adc_trigger_list[i];
2386 if (!st->selected_trig) {
2391 init_waitqueue_head(&st->wq_data_available);
2392 mutex_init(&st->lock);
2393 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler);
2395 st->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2396 if (IS_ERR(st->base))
2397 return PTR_ERR(st->base);
2400 st->dma_st.phys_addr = res->start;
2402 st->irq = platform_get_irq(pdev, 0);
2403 if (st->irq < 0)
2404 return st->irq;
2406 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
2407 if (IS_ERR(st->per_clk))
2408 return PTR_ERR(st->per_clk);
2410 st->reg = devm_regulator_get(&pdev->dev, "vddana");
2411 if (IS_ERR(st->reg))
2412 return PTR_ERR(st->reg);
2414 st->vref = devm_regulator_get(&pdev->dev, "vref");
2415 if (IS_ERR(st->vref))
2416 return PTR_ERR(st->vref);
2418 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
2423 ret = regulator_enable(st->reg);
2427 ret = regulator_enable(st->vref);
2431 st->vref_uv = regulator_get_voltage(st->vref);
2432 if (st->vref_uv <= 0) {
2437 ret = clk_prepare_enable(st->per_clk);
2442 st->dev = &pdev->dev;
2443 pm_runtime_set_autosuspend_delay(st->dev, 500);
2444 pm_runtime_use_autosuspend(st->dev);
2445 pm_runtime_set_active(st->dev);
2446 pm_runtime_enable(st->dev);
2447 pm_runtime_get_noresume(st->dev);
2462 if (st->selected_trig->hw_trig)
2464 st->selected_trig->name);
2467 readl_relaxed(st->base + st->soc_info.platform->layout->VERSION));
2469 pm_runtime_mark_last_busy(st->dev);
2470 pm_runtime_put_autosuspend(st->dev);
2475 at91_adc_dma_disable(st);
2477 pm_runtime_put_noidle(st->dev);
2478 pm_runtime_disable(st->dev);
2479 pm_runtime_set_suspended(st->dev);
2480 pm_runtime_dont_use_autosuspend(st->dev);
2481 clk_disable_unprepare(st->per_clk);
2483 regulator_disable(st->vref);
2485 regulator_disable(st->reg);
2492 struct at91_adc_state *st = iio_priv(indio_dev);
2496 at91_adc_dma_disable(st);
2498 pm_runtime_disable(st->dev);
2499 pm_runtime_set_suspended(st->dev);
2500 clk_disable_unprepare(st->per_clk);
2502 regulator_disable(st->vref);
2503 regulator_disable(st->reg);
2511 struct at91_adc_state *st = iio_priv(indio_dev);
2514 ret = pm_runtime_resume_and_get(st->dev);
2527 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST);
2529 pm_runtime_mark_last_busy(st->dev);
2530 pm_runtime_put_noidle(st->dev);
2531 clk_disable_unprepare(st->per_clk);
2532 regulator_disable(st->vref);
2533 regulator_disable(st->reg);
2541 struct at91_adc_state *st = iio_priv(indio_dev);
2548 ret = regulator_enable(st->reg);
2552 ret = regulator_enable(st->vref);
2556 ret = clk_prepare_enable(st->per_clk);
2560 pm_runtime_get_noresume(st->dev);
2570 at91_adc_configure_trigger_registers(st, true);
2573 pm_runtime_mark_last_busy(st->dev);
2574 pm_runtime_put_autosuspend(st->dev);
2579 pm_runtime_mark_last_busy(st->dev);
2580 pm_runtime_put_noidle(st->dev);
2581 clk_disable_unprepare(st->per_clk);
2583 regulator_disable(st->vref);
2585 regulator_disable(st->reg);
2594 struct at91_adc_state *st = iio_priv(indio_dev);
2596 clk_disable(st->per_clk);
2604 struct at91_adc_state *st = iio_priv(indio_dev);
2606 return clk_enable(st->per_clk);