Lines Matching defs:dma_st
601 struct at91_adc_dma dma_st;
1155 if (st->dma_st.dma_chan)
1176 status = dmaengine_tx_status(st->dma_st.dma_chan,
1177 st->dma_st.dma_chan->cookie,
1183 i = st->dma_st.rx_buf_sz - state.residue;
1186 if (i >= st->dma_st.buf_idx)
1187 size = i - st->dma_st.buf_idx;
1189 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx;
1208 if (!st->dma_st.dma_chan)
1212 st->dma_st.buf_idx = 0;
1218 st->dma_st.rx_buf_sz = 0;
1228 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8;
1230 st->dma_st.rx_buf_sz *= st->dma_st.watermark;
1233 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan,
1234 st->dma_st.rx_dma_buf,
1235 st->dma_st.rx_buf_sz,
1236 st->dma_st.rx_buf_sz / 2,
1251 dmaengine_terminate_async(st->dma_st.dma_chan);
1258 dma_async_issue_pending(st->dma_st.dma_chan);
1261 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1272 if (st->dma_st.dma_chan)
1379 if (st->dma_st.dma_chan)
1390 if (st->dma_st.dma_chan)
1391 dmaengine_terminate_sync(st->dma_st.dma_chan);
1496 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark);
1504 interval = div_s64((ns - st->dma_st.dma_ts), sample_count);
1512 &st->dma_st.rx_buf[st->dma_st.buf_idx],
1516 (st->dma_st.rx_buf + st->dma_st.buf_idx),
1517 (st->dma_st.dma_ts + interval * sample_index));
1521 st->dma_st.buf_idx += sample_size;
1523 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz)
1524 st->dma_st.buf_idx = 0;
1528 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1544 if (st->dma_st.dma_chan)
1720 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) {
2030 if (st->dma_st.dma_chan)
2033 st->dma_st.dma_chan = dma_request_chan(dev, "rx");
2034 if (IS_ERR(st->dma_st.dma_chan)) {
2036 st->dma_st.dma_chan = NULL;
2040 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev,
2042 &st->dma_st.rx_dma_buf,
2044 if (!st->dma_st.rx_buf) {
2051 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr
2057 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) {
2063 dma_chan_name(st->dma_st.dma_chan));
2068 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
2069 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
2071 dma_release_channel(st->dma_st.dma_chan);
2072 st->dma_st.dma_chan = NULL;
2086 if (!st->dma_st.dma_chan)
2090 dmaengine_terminate_sync(st->dma_st.dma_chan);
2092 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
2093 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
2094 dma_release_channel(st->dma_st.dma_chan);
2095 st->dma_st.dma_chan = NULL;
2114 st->dma_st.watermark = val;
2184 return sysfs_emit(buf, "%d\n", !!st->dma_st.dma_chan);
2193 return sysfs_emit(buf, "%d\n", st->dma_st.watermark);
2254 st->dma_st.watermark = 1;
2400 st->dma_st.phys_addr = res->start;