Lines Matching refs:ad7949_adc
93 static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val,
98 ad7949_adc->cfg = (val & mask) | (ad7949_adc->cfg & ~mask);
100 switch (ad7949_adc->spi->bits_per_word) {
102 ad7949_adc->buffer = ad7949_adc->cfg << 2;
103 ret = spi_write(ad7949_adc->spi, &ad7949_adc->buffer, 2);
106 ad7949_adc->buffer = ad7949_adc->cfg;
107 ret = spi_write(ad7949_adc->spi, &ad7949_adc->buffer, 2);
111 ad7949_adc->buf8b = cpu_to_be16(ad7949_adc->cfg << 2);
112 ret = spi_write(ad7949_adc->spi, &ad7949_adc->buf8b, 2);
115 dev_err(&ad7949_adc->indio_dev->dev, "unsupported BPW\n");
127 static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val,
140 ret = ad7949_spi_write_cfg(ad7949_adc,
145 if (channel == ad7949_adc->current_channel)
150 if (ad7949_adc->spi->bits_per_word == 8)
151 ret = spi_read(ad7949_adc->spi, &ad7949_adc->buf8b, 2);
153 ret = spi_read(ad7949_adc->spi, &ad7949_adc->buffer, 2);
164 ad7949_adc->current_channel = channel;
166 switch (ad7949_adc->spi->bits_per_word) {
168 *val = ad7949_adc->buffer;
170 *val >>= 16 - ad7949_adc->resolution;
173 *val = ad7949_adc->buffer & GENMASK(13, 0);
177 *val = be16_to_cpu(ad7949_adc->buf8b);
179 *val >>= 16 - ad7949_adc->resolution;
182 dev_err(&ad7949_adc->indio_dev->dev, "unsupported BPW\n");
212 struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
220 mutex_lock(&ad7949_adc->lock);
221 ret = ad7949_spi_read_channel(ad7949_adc, val, chan->channel);
222 mutex_unlock(&ad7949_adc->lock);
230 switch (ad7949_adc->refsel) {
239 ret = regulator_get_voltage(ad7949_adc->vref);
248 *val2 = (1 << ad7949_adc->resolution) - 1;
259 struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
263 *readval = ad7949_adc->cfg;
265 ret = ad7949_spi_write_cfg(ad7949_adc, writeval,
276 static int ad7949_spi_init(struct ad7949_adc_chip *ad7949_adc)
282 ad7949_adc->current_channel = 0;
286 FIELD_PREP(AD7949_CFG_MASK_INX, ad7949_adc->current_channel) |
288 FIELD_PREP(AD7949_CFG_MASK_REF, ad7949_adc->refsel) |
292 ret = ad7949_spi_write_cfg(ad7949_adc, cfg, AD7949_CFG_MASK_TOTAL);
298 ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel);
299 ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel);
314 struct ad7949_adc_chip *ad7949_adc;
319 indio_dev = devm_iio_device_alloc(dev, sizeof(*ad7949_adc));
331 ad7949_adc = iio_priv(indio_dev);
332 ad7949_adc->indio_dev = indio_dev;
333 ad7949_adc->spi = spi;
337 ad7949_adc->resolution = spec->resolution;
340 if (spi_ctrl_mask & SPI_BPW_MASK(ad7949_adc->resolution)) {
341 spi->bits_per_word = ad7949_adc->resolution;
357 ad7949_adc->refsel = AD7949_CFG_VAL_REF_INT_2500;
360 ad7949_adc->refsel = AD7949_CFG_VAL_REF_INT_4096;
368 ad7949_adc->vref = devm_regulator_get_optional(dev, "vrefin");
369 if (IS_ERR(ad7949_adc->vref)) {
370 ret = PTR_ERR(ad7949_adc->vref);
374 ad7949_adc->vref = devm_regulator_get_optional(dev, "vref");
375 if (IS_ERR(ad7949_adc->vref)) {
376 ret = PTR_ERR(ad7949_adc->vref);
380 ad7949_adc->refsel = AD7949_CFG_VAL_REF_EXT_TEMP;
383 ad7949_adc->refsel = AD7949_CFG_VAL_REF_EXT_TEMP_BUF;
386 if (ad7949_adc->refsel & AD7949_CFG_VAL_REF_EXTERNAL) {
387 ret = regulator_enable(ad7949_adc->vref);
394 ad7949_adc->vref);
399 mutex_init(&ad7949_adc->lock);
401 ret = ad7949_spi_init(ad7949_adc);