Lines Matching refs:fclk
262 unsigned int fclk, odr_sel_bits;
264 fclk = clk_get_rate(st->mclk);
272 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
282 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
891 unsigned int fclk, power_mode;
894 fclk = clk_get_rate(st->mclk);
895 if (!fclk)
901 fclk);
902 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
903 ret = clk_set_rate(st->mclk, fclk);