Lines Matching refs:mclk_sel
289 u32 mclk_sel;
1687 st->mclk_sel = AD4130_MCLK_153_6KHZ_EXT;
1689 st->mclk_sel = AD4130_MCLK_76_8KHZ_EXT;
1691 st->mclk_sel = AD4130_MCLK_76_8KHZ;
1694 st->mclk_sel != AD4130_MCLK_76_8KHZ)
1697 st->mclk_sel, st->int_pin_sel);
1766 enum ad4130_mclk_sel mclk_sel)
1771 mclk_sel));
1784 return st->mclk_sel == AD4130_MCLK_76_8KHZ_OUT;
1796 st->mclk_sel = AD4130_MCLK_76_8KHZ_OUT;
1810 st->mclk_sel = AD4130_MCLK_76_8KHZ;
1835 st->mclk_sel != AD4130_MCLK_76_8KHZ)
1869 if (st->mclk_sel == AD4130_MCLK_153_6KHZ_EXT)
1895 val |= FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, st->mclk_sel);