Lines Matching defs:master
3 * Silvaco dual-role I3C master driver
14 #include <linux/i3c/master.h>
157 * @base: I3C master controller
179 * @lock: Transfer lock, protect between IBI work thread and callbacks from master
213 * @index: Index in the master tables corresponding to this device
214 * @ibi: IBI slot index in the master structure
223 static bool svc_i3c_master_error(struct svc_i3c_master *master)
227 mstatus = readl(master->regs + SVC_I3C_MSTATUS);
229 merrwarn = readl(master->regs + SVC_I3C_MERRWARN);
230 writel(merrwarn, master->regs + SVC_I3C_MERRWARN);
234 dev_dbg(master->dev, "Warning condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n",
239 dev_err(master->dev,
249 static void svc_i3c_master_enable_interrupts(struct svc_i3c_master *master, u32 mask)
251 writel(mask, master->regs + SVC_I3C_MINTSET);
254 static void svc_i3c_master_disable_interrupts(struct svc_i3c_master *master)
256 u32 mask = readl(master->regs + SVC_I3C_MINTSET);
258 writel(mask, master->regs + SVC_I3C_MINTCLR);
261 static void svc_i3c_master_clear_merrwarn(struct svc_i3c_master *master)
264 writel(readl(master->regs + SVC_I3C_MERRWARN),
265 master->regs + SVC_I3C_MERRWARN);
268 static void svc_i3c_master_flush_fifo(struct svc_i3c_master *master)
272 master->regs + SVC_I3C_MDATACTRL);
275 static void svc_i3c_master_reset_fifo_trigger(struct svc_i3c_master *master)
285 writel(reg, master->regs + SVC_I3C_MDATACTRL);
288 static void svc_i3c_master_reset(struct svc_i3c_master *master)
290 svc_i3c_master_clear_merrwarn(master);
291 svc_i3c_master_reset_fifo_trigger(master);
292 svc_i3c_master_disable_interrupts(master);
296 to_svc_i3c_master(struct i3c_master_controller *master)
298 return container_of(master, struct svc_i3c_master, base);
303 struct svc_i3c_master *master;
305 master = container_of(work, struct svc_i3c_master, hj_work);
306 i3c_master_do_daa(&master->base);
310 svc_i3c_master_dev_from_addr(struct svc_i3c_master *master,
316 if (master->addrs[i] == ibiaddr)
322 return master->descs[i];
325 static void svc_i3c_master_emit_stop(struct svc_i3c_master *master)
327 writel(SVC_I3C_MCTRL_REQUEST_STOP, master->regs + SVC_I3C_MCTRL);
338 static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master,
355 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
358 dev_err(master->dev, "Timeout when polling for COMPLETE\n");
362 while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) &&
364 mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL);
366 readsl(master->regs + SVC_I3C_MRDATAB, buf, count);
371 master->ibi.tbq_slot = slot;
376 static void svc_i3c_master_ack_ibi(struct svc_i3c_master *master,
387 writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL);
390 static void svc_i3c_master_nack_ibi(struct svc_i3c_master *master)
394 master->regs + SVC_I3C_MCTRL);
399 struct svc_i3c_master *master = container_of(work, struct svc_i3c_master, ibi_work);
406 mutex_lock(&master->lock);
410 master->regs + SVC_I3C_MCTRL);
413 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
416 dev_err(master->dev, "Timeout when polling for IBIWON\n");
417 svc_i3c_master_emit_stop(master);
422 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
424 status = readl(master->regs + SVC_I3C_MSTATUS);
431 dev = svc_i3c_master_dev_from_addr(master, ibiaddr);
433 svc_i3c_master_nack_ibi(master);
435 svc_i3c_master_handle_ibi(master, dev);
438 svc_i3c_master_ack_ibi(master, false);
441 svc_i3c_master_nack_ibi(master);
452 if (svc_i3c_master_error(master)) {
453 if (master->ibi.tbq_slot) {
456 master->ibi.tbq_slot);
457 master->ibi.tbq_slot = NULL;
460 svc_i3c_master_emit_stop(master);
469 i3c_master_queue_ibi(dev, master->ibi.tbq_slot);
470 master->ibi.tbq_slot = NULL;
472 svc_i3c_master_emit_stop(master);
475 queue_work(master->base.wq, &master->hj_work);
483 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
484 mutex_unlock(&master->lock);
489 struct svc_i3c_master *master = (struct svc_i3c_master *)dev_id;
490 u32 active = readl(master->regs + SVC_I3C_MSTATUS);
496 writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
498 svc_i3c_master_disable_interrupts(master);
501 queue_work(master->base.wq, &master->ibi_work);
508 struct svc_i3c_master *master = to_svc_i3c_master(m);
516 ret = pm_runtime_resume_and_get(master->dev);
518 dev_err(master->dev,
519 "<%s> cannot resume i3c bus master, err: %d\n",
525 fclk_rate = clk_get_rate(master->fclk);
586 writel(reg, master->regs + SVC_I3C_MCONFIG);
596 master->regs + SVC_I3C_MDYNADDR);
598 ret = i3c_master_set_info(&master->base, &info);
603 pm_runtime_mark_last_busy(master->dev);
604 pm_runtime_put_autosuspend(master->dev);
611 struct svc_i3c_master *master = to_svc_i3c_master(m);
614 ret = pm_runtime_resume_and_get(master->dev);
616 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
620 svc_i3c_master_disable_interrupts(master);
622 /* Disable master */
623 writel(0, master->regs + SVC_I3C_MCONFIG);
625 pm_runtime_mark_last_busy(master->dev);
626 pm_runtime_put_autosuspend(master->dev);
629 static int svc_i3c_master_reserve_slot(struct svc_i3c_master *master)
633 if (!(master->free_slots & GENMASK(SVC_I3C_MAX_DEVS - 1, 0)))
636 slot = ffs(master->free_slots) - 1;
638 master->free_slots &= ~BIT(slot);
643 static void svc_i3c_master_release_slot(struct svc_i3c_master *master,
646 master->free_slots |= BIT(slot);
652 struct svc_i3c_master *master = to_svc_i3c_master(m);
656 slot = svc_i3c_master_reserve_slot(master);
662 svc_i3c_master_release_slot(master, slot);
668 master->addrs[slot] = dev->info.dyn_addr ? dev->info.dyn_addr :
670 master->descs[slot] = dev;
681 struct svc_i3c_master *master = to_svc_i3c_master(m);
684 master->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr :
694 struct svc_i3c_master *master = to_svc_i3c_master(m);
696 master->addrs[data->index] = 0;
697 svc_i3c_master_release_slot(master, data->index);
705 struct svc_i3c_master *master = to_svc_i3c_master(m);
709 slot = svc_i3c_master_reserve_slot(master);
715 svc_i3c_master_release_slot(master, slot);
720 master->addrs[slot] = dev->addr;
731 struct svc_i3c_master *master = to_svc_i3c_master(m);
733 svc_i3c_master_release_slot(master, data->index);
738 static int svc_i3c_master_readb(struct svc_i3c_master *master, u8 *dst,
745 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
752 dst[i] = readl(master->regs + SVC_I3C_MRDATAB);
758 static int svc_i3c_master_do_daa_locked(struct svc_i3c_master *master,
772 master->regs + SVC_I3C_MCTRL);
778 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
794 ret = svc_i3c_master_readb(master, data, 6);
802 ret = svc_i3c_master_readb(master, data, 2);
831 svc_i3c_master_emit_stop(master);
840 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
850 ret = i3c_master_get_free_addr(&master->base, last_addr + 1);
855 dev_dbg(master->dev, "DAA: device %d assigned to 0x%02x\n",
858 writel(addrs[dev_nb], master->regs + SVC_I3C_MWDATAB);
867 static int svc_i3c_update_ibirules(struct svc_i3c_master *master)
876 i3c_bus_for_each_i3cdev(&master->base.bus, dev) {
914 writel(reg_mbyte, master->regs + SVC_I3C_IBIRULES);
916 writel(reg_nobyte, master->regs + SVC_I3C_IBIRULES);
923 struct svc_i3c_master *master = to_svc_i3c_master(m);
929 ret = pm_runtime_resume_and_get(master->dev);
931 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
935 spin_lock_irqsave(&master->xferqueue.lock, flags);
936 ret = svc_i3c_master_do_daa_locked(master, addrs, &dev_nb);
937 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
939 svc_i3c_master_emit_stop(master);
940 svc_i3c_master_clear_merrwarn(master);
952 ret = svc_i3c_update_ibirules(master);
954 dev_err(master->dev, "Cannot handle such a list of devices");
957 pm_runtime_mark_last_busy(master->dev);
958 pm_runtime_put_autosuspend(master->dev);
963 static int svc_i3c_master_read(struct svc_i3c_master *master,
973 mstatus = readl(master->regs + SVC_I3C_MSTATUS);
978 dev_dbg(master->dev, "I3C read timeout\n");
982 mdctrl = readl(master->regs + SVC_I3C_MDATACTRL);
985 dev_err(master->dev, "I3C receive length too long!\n");
989 in[offset + i] = readl(master->regs + SVC_I3C_MRDATAB);
997 static int svc_i3c_master_write(struct svc_i3c_master *master,
1004 ret = readl_poll_timeout(master->regs + SVC_I3C_MDATACTRL,
1016 writel(out[offset++], master->regs + SVC_I3C_MWDATAB);
1018 writel(out[offset++], master->regs + SVC_I3C_MWDATABE);
1024 static int svc_i3c_master_xfer(struct svc_i3c_master *master,
1033 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
1041 master->regs + SVC_I3C_MCTRL);
1043 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1048 if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) {
1071 ret = svc_i3c_master_read(master, in, xfer_len);
1073 ret = svc_i3c_master_write(master, out, xfer_len);
1080 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1085 writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS);
1088 svc_i3c_master_emit_stop(master);
1091 readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1098 svc_i3c_master_emit_stop(master);
1099 svc_i3c_master_clear_merrwarn(master);
1105 svc_i3c_master_alloc_xfer(struct svc_i3c_master *master, unsigned int ncmds)
1125 static void svc_i3c_master_dequeue_xfer_locked(struct svc_i3c_master *master,
1128 if (master->xferqueue.cur == xfer)
1129 master->xferqueue.cur = NULL;
1134 static void svc_i3c_master_dequeue_xfer(struct svc_i3c_master *master,
1139 spin_lock_irqsave(&master->xferqueue.lock, flags);
1140 svc_i3c_master_dequeue_xfer_locked(master, xfer);
1141 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
1144 static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master)
1146 struct svc_i3c_xfer *xfer = master->xferqueue.cur;
1152 svc_i3c_master_clear_merrwarn(master);
1153 svc_i3c_master_flush_fifo(master);
1158 ret = svc_i3c_master_xfer(master, cmd->rnw, xfer->type,
1170 svc_i3c_master_dequeue_xfer_locked(master, xfer);
1172 xfer = list_first_entry_or_null(&master->xferqueue.list,
1178 master->xferqueue.cur = xfer;
1179 svc_i3c_master_start_xfer_locked(master);
1182 static void svc_i3c_master_enqueue_xfer(struct svc_i3c_master *master,
1188 ret = pm_runtime_resume_and_get(master->dev);
1190 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1195 spin_lock_irqsave(&master->xferqueue.lock, flags);
1196 if (master->xferqueue.cur) {
1197 list_add_tail(&xfer->node, &master->xferqueue.list);
1199 master->xferqueue.cur = xfer;
1200 svc_i3c_master_start_xfer_locked(master);
1202 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
1204 pm_runtime_mark_last_busy(master->dev);
1205 pm_runtime_put_autosuspend(master->dev);
1209 svc_i3c_master_supports_ccc_cmd(struct i3c_master_controller *master,
1216 static int svc_i3c_master_send_bdcast_ccc_cmd(struct svc_i3c_master *master,
1225 xfer = svc_i3c_master_alloc_xfer(master, 1);
1249 mutex_lock(&master->lock);
1250 svc_i3c_master_enqueue_xfer(master, xfer);
1252 svc_i3c_master_dequeue_xfer(master, xfer);
1253 mutex_unlock(&master->lock);
1262 static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master,
1271 xfer = svc_i3c_master_alloc_xfer(master, 2);
1297 mutex_lock(&master->lock);
1298 svc_i3c_master_enqueue_xfer(master, xfer);
1300 svc_i3c_master_dequeue_xfer(master, xfer);
1301 mutex_unlock(&master->lock);
1315 struct svc_i3c_master *master = to_svc_i3c_master(m);
1320 ret = svc_i3c_master_send_bdcast_ccc_cmd(master, cmd);
1322 ret = svc_i3c_master_send_direct_ccc_cmd(master, cmd);
1335 struct svc_i3c_master *master = to_svc_i3c_master(m);
1340 xfer = svc_i3c_master_alloc_xfer(master, nxfers);
1349 cmd->addr = master->addrs[data->index];
1358 mutex_lock(&master->lock);
1359 svc_i3c_master_enqueue_xfer(master, xfer);
1361 svc_i3c_master_dequeue_xfer(master, xfer);
1362 mutex_unlock(&master->lock);
1375 struct svc_i3c_master *master = to_svc_i3c_master(m);
1380 xfer = svc_i3c_master_alloc_xfer(master, nxfers);
1389 cmd->addr = master->addrs[data->index];
1398 mutex_lock(&master->lock);
1399 svc_i3c_master_enqueue_xfer(master, xfer);
1401 svc_i3c_master_dequeue_xfer(master, xfer);
1402 mutex_unlock(&master->lock);
1414 struct svc_i3c_master *master = to_svc_i3c_master(m);
1420 dev_err(master->dev, "IBI max payload %d should be < %d\n",
1429 spin_lock_irqsave(&master->ibi.lock, flags);
1430 for (i = 0; i < master->ibi.num_slots; i++) {
1431 if (!master->ibi.slots[i]) {
1433 master->ibi.slots[i] = dev;
1437 spin_unlock_irqrestore(&master->ibi.lock, flags);
1439 if (i < master->ibi.num_slots)
1451 struct svc_i3c_master *master = to_svc_i3c_master(m);
1455 spin_lock_irqsave(&master->ibi.lock, flags);
1456 master->ibi.slots[data->ibi] = NULL;
1458 spin_unlock_irqrestore(&master->ibi.lock, flags);
1466 struct svc_i3c_master *master = to_svc_i3c_master(m);
1469 ret = pm_runtime_resume_and_get(master->dev);
1471 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1475 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
1483 struct svc_i3c_master *master = to_svc_i3c_master(m);
1486 svc_i3c_master_disable_interrupts(master);
1490 pm_runtime_mark_last_busy(master->dev);
1491 pm_runtime_put_autosuspend(master->dev);
1524 static int svc_i3c_master_prepare_clks(struct svc_i3c_master *master)
1528 ret = clk_prepare_enable(master->pclk);
1532 ret = clk_prepare_enable(master->fclk);
1534 clk_disable_unprepare(master->pclk);
1538 ret = clk_prepare_enable(master->sclk);
1540 clk_disable_unprepare(master->pclk);
1541 clk_disable_unprepare(master->fclk);
1548 static void svc_i3c_master_unprepare_clks(struct svc_i3c_master *master)
1550 clk_disable_unprepare(master->pclk);
1551 clk_disable_unprepare(master->fclk);
1552 clk_disable_unprepare(master->sclk);
1558 struct svc_i3c_master *master;
1561 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
1562 if (!master)
1565 master->regs = devm_platform_ioremap_resource(pdev, 0);
1566 if (IS_ERR(master->regs))
1567 return PTR_ERR(master->regs);
1569 master->pclk = devm_clk_get(dev, "pclk");
1570 if (IS_ERR(master->pclk))
1571 return PTR_ERR(master->pclk);
1573 master->fclk = devm_clk_get(dev, "fast_clk");
1574 if (IS_ERR(master->fclk))
1575 return PTR_ERR(master->fclk);
1577 master->sclk = devm_clk_get(dev, "slow_clk");
1578 if (IS_ERR(master->sclk))
1579 return PTR_ERR(master->sclk);
1581 master->irq = platform_get_irq(pdev, 0);
1582 if (master->irq < 0)
1583 return master->irq;
1585 master->dev = dev;
1587 ret = svc_i3c_master_prepare_clks(master);
1591 INIT_WORK(&master->hj_work, svc_i3c_master_hj_work);
1592 INIT_WORK(&master->ibi_work, svc_i3c_master_ibi_work);
1593 mutex_init(&master->lock);
1595 ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler,
1596 IRQF_NO_SUSPEND, "svc-i3c-irq", master);
1600 master->free_slots = GENMASK(SVC_I3C_MAX_DEVS - 1, 0);
1602 spin_lock_init(&master->xferqueue.lock);
1603 INIT_LIST_HEAD(&master->xferqueue.list);
1605 spin_lock_init(&master->ibi.lock);
1606 master->ibi.num_slots = SVC_I3C_MAX_DEVS;
1607 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots,
1608 sizeof(*master->ibi.slots),
1610 if (!master->ibi.slots) {
1615 platform_set_drvdata(pdev, master);
1623 svc_i3c_master_reset(master);
1625 /* Register the master */
1626 ret = i3c_master_register(&master->base, &pdev->dev,
1643 svc_i3c_master_unprepare_clks(master);
1650 struct svc_i3c_master *master = platform_get_drvdata(pdev);
1652 i3c_master_unregister(&master->base);
1658 static void svc_i3c_save_regs(struct svc_i3c_master *master)
1660 master->saved_regs.mconfig = readl(master->regs + SVC_I3C_MCONFIG);
1661 master->saved_regs.mdynaddr = readl(master->regs + SVC_I3C_MDYNADDR);
1664 static void svc_i3c_restore_regs(struct svc_i3c_master *master)
1666 if (readl(master->regs + SVC_I3C_MDYNADDR) !=
1667 master->saved_regs.mdynaddr) {
1668 writel(master->saved_regs.mconfig,
1669 master->regs + SVC_I3C_MCONFIG);
1670 writel(master->saved_regs.mdynaddr,
1671 master->regs + SVC_I3C_MDYNADDR);
1677 struct svc_i3c_master *master = dev_get_drvdata(dev);
1679 svc_i3c_save_regs(master);
1680 svc_i3c_master_unprepare_clks(master);
1688 struct svc_i3c_master *master = dev_get_drvdata(dev);
1691 svc_i3c_master_prepare_clks(master);
1693 svc_i3c_restore_regs(master);
1706 { .compatible = "silvaco,i3c-master" },
1715 .name = "silvaco-i3c-master",
1724 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver");