Lines Matching defs:SVC_I3C_MSTATUS
58 #define SVC_I3C_MSTATUS 0x088
227 mstatus = readl(master->regs + SVC_I3C_MSTATUS);
355 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
362 while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) &&
413 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
422 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
424 status = readl(master->regs + SVC_I3C_MSTATUS);
490 u32 active = readl(master->regs + SVC_I3C_MSTATUS);
496 writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
745 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
778 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
840 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
973 mstatus = readl(master->regs + SVC_I3C_MSTATUS);
1033 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
1043 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1080 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1085 writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS);
1091 readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,