Lines Matching defs:i2c_dev
302 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
305 writel_relaxed(val, i2c_dev->base + reg);
308 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
310 return readl_relaxed(i2c_dev->base + reg);
317 static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
319 if (IS_DVC(i2c_dev))
321 else if (IS_VI(i2c_dev))
327 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg)
329 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
333 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
334 else if (IS_VI(i2c_dev))
335 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS));
338 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
340 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
343 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
346 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
349 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data,
361 i2c_writel(i2c_dev, *data32++, reg);
364 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
367 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
370 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
374 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
375 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
378 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
382 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
383 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
388 struct tegra_i2c_dev *i2c_dev = args;
390 complete(&i2c_dev->dma_complete);
393 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
398 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
400 reinit_completion(&i2c_dev->dma_complete);
402 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
404 dma_desc = dmaengine_prep_slave_single(i2c_dev->dma_chan, i2c_dev->dma_phys,
408 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n",
409 i2c_dev->msg_read ? "RX" : "TX");
414 dma_desc->callback_param = i2c_dev;
417 dma_async_issue_pending(i2c_dev->dma_chan);
422 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
424 if (i2c_dev->dma_buf) {
425 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
426 i2c_dev->dma_buf, i2c_dev->dma_phys);
427 i2c_dev->dma_buf = NULL;
430 if (i2c_dev->dma_chan) {
431 dma_release_channel(i2c_dev->dma_chan);
432 i2c_dev->dma_chan = NULL;
436 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
442 if (IS_VI(i2c_dev))
445 if (i2c_dev->hw->has_apb_dma) {
447 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n");
451 dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n");
460 i2c_dev->dma_chan = dma_request_chan(i2c_dev->dev, "tx");
461 if (IS_ERR(i2c_dev->dma_chan)) {
462 err = PTR_ERR(i2c_dev->dma_chan);
463 i2c_dev->dma_chan = NULL;
467 i2c_dev->dma_dev = i2c_dev->dma_chan->device->dev;
468 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +
471 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
474 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n");
479 i2c_dev->dma_buf = dma_buf;
480 i2c_dev->dma_phys = dma_phys;
485 tegra_i2c_release_dma(i2c_dev);
487 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
488 dev_err(i2c_dev->dev, "falling back to PIO\n");
502 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
506 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
509 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
511 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
513 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
516 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
522 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0);
528 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1);
532 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0);
537 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1);
540 i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG);
542 i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
545 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
549 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg);
552 if (!i2c_dev->atomic_mode)
560 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
565 if (i2c_dev->hw->has_mst_fifo) {
575 val = i2c_readl(i2c_dev, offset);
577 i2c_writel(i2c_dev, val, offset);
579 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000);
581 dev_err(i2c_dev->dev, "failed to flush FIFO\n");
588 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
592 if (!i2c_dev->hw->has_config_load_reg)
595 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
597 err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff,
600 dev_err(i2c_dev->dev, "failed to load config\n");
607 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
610 acpi_handle handle = ACPI_HANDLE(i2c_dev->dev);
611 struct i2c_timings *t = &i2c_dev->timings;
625 err = reset_control_reset(i2c_dev->rst);
629 if (IS_DVC(i2c_dev))
630 tegra_dvc_init(i2c_dev);
635 if (i2c_dev->hw->has_multi_master_mode)
638 i2c_writel(i2c_dev, val, I2C_CNFG);
639 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
641 if (IS_VI(i2c_dev))
642 tegra_i2c_vi_init(i2c_dev);
647 tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
648 thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
649 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
652 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
654 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
658 tlow = i2c_dev->hw->tlow_std_mode;
659 thigh = i2c_dev->hw->thigh_std_mode;
660 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
661 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
667 i2c_dev->hw->clk_divisor_hs_mode) |
669 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
671 if (i2c_dev->hw->has_interface_timing_reg) {
674 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
681 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
682 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
686 err = clk_set_rate(i2c_dev->div_clk,
689 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
693 if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) {
694 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
697 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
698 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
699 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
702 err = tegra_i2c_flush_fifos(i2c_dev);
706 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
707 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
709 err = tegra_i2c_wait_for_config_load(i2c_dev);
716 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
726 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz));
728 cnfg = i2c_readl(i2c_dev, I2C_CNFG);
730 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
732 return tegra_i2c_wait_for_config_load(i2c_dev);
735 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
737 size_t buf_remaining = i2c_dev->msg_buf_remaining;
739 u8 *buf = i2c_dev->msg_buf;
746 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
749 if (i2c_dev->hw->has_mst_fifo) {
750 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
753 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
762 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
778 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
789 i2c_dev->msg_buf_remaining = buf_remaining;
790 i2c_dev->msg_buf = buf;
795 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
797 size_t buf_remaining = i2c_dev->msg_buf_remaining;
799 u8 *buf = i2c_dev->msg_buf;
802 if (i2c_dev->hw->has_mst_fifo) {
803 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
806 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
833 i2c_dev->msg_buf_remaining = buf_remaining;
834 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD;
836 if (IS_VI(i2c_dev))
837 i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
839 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
858 i2c_dev->msg_buf_remaining = 0;
859 i2c_dev->msg_buf = NULL;
861 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
870 struct tegra_i2c_dev *i2c_dev = dev_id;
873 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
876 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n",
877 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
878 i2c_readl(i2c_dev, I2C_STATUS),
879 i2c_readl(i2c_dev, I2C_CNFG));
880 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
885 tegra_i2c_disable_packet_mode(i2c_dev);
887 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
889 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
897 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
900 if (!i2c_dev->dma_mode) {
901 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
902 if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
908 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
913 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
914 if (i2c_dev->msg_buf_remaining)
915 tegra_i2c_fill_tx_fifo(i2c_dev);
917 tegra_i2c_mask_irq(i2c_dev,
922 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
923 if (IS_DVC(i2c_dev))
924 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
935 if (i2c_dev->dma_mode)
936 i2c_dev->msg_buf_remaining = 0;
941 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
942 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
945 complete(&i2c_dev->msg_complete);
950 tegra_i2c_mask_irq(i2c_dev,
957 if (i2c_dev->hw->supports_bus_clear)
958 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
960 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
962 if (IS_DVC(i2c_dev))
963 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
965 if (i2c_dev->dma_mode) {
966 dmaengine_terminate_async(i2c_dev->dma_chan);
967 complete(&i2c_dev->dma_complete);
970 complete(&i2c_dev->msg_complete);
975 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
982 if (i2c_dev->hw->has_mst_fifo)
987 if (i2c_dev->dma_mode) {
995 if (i2c_dev->msg_read) {
996 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
998 slv_config.src_addr = i2c_dev->base_phys + reg_offset;
1002 if (i2c_dev->hw->has_mst_fifo)
1007 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
1009 slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
1013 if (i2c_dev->hw->has_mst_fifo)
1020 err = dmaengine_slave_config(i2c_dev->dma_chan, &slv_config);
1022 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err);
1023 dev_err(i2c_dev->dev, "falling back to PIO\n");
1025 tegra_i2c_release_dma(i2c_dev);
1026 i2c_dev->dma_mode = false;
1032 if (i2c_dev->hw->has_mst_fifo)
1039 i2c_writel(i2c_dev, val, reg);
1042 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev,
1050 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1053 tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1068 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev,
1074 if (i2c_dev->atomic_mode) {
1075 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms);
1077 enable_irq(i2c_dev->irq);
1080 disable_irq(i2c_dev->irq);
1093 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0);
1101 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1105 reinit_completion(&i2c_dev->msg_complete);
1109 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1111 err = tegra_i2c_wait_for_config_load(i2c_dev);
1116 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1117 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1119 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50);
1120 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1123 dev_err(i2c_dev->dev, "failed to clear bus\n");
1127 val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1129 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n");
1136 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
1140 u32 *dma_buf = i2c_dev->dma_buf;
1146 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
1149 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1152 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1154 packet_header = i2c_dev->msg_len - 1;
1156 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1159 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1181 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1184 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1187 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev,
1190 if (i2c_dev->msg_err == I2C_ERR_NONE)
1193 tegra_i2c_init(i2c_dev);
1196 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1197 if (!i2c_dev->multimaster_mode)
1198 return i2c_recover_bus(&i2c_dev->adapter);
1203 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1213 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1222 err = tegra_i2c_flush_fifos(i2c_dev);
1226 i2c_dev->msg_buf = msg->buf;
1227 i2c_dev->msg_len = msg->len;
1229 i2c_dev->msg_err = I2C_ERR_NONE;
1230 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD);
1231 reinit_completion(&i2c_dev->msg_complete);
1240 i2c_dev->msg_len = 1;
1242 i2c_dev->msg_buf += 1;
1243 i2c_dev->msg_len -= 1;
1247 i2c_dev->msg_buf_remaining = i2c_dev->msg_len;
1249 if (i2c_dev->msg_read)
1250 xfer_size = i2c_dev->msg_len;
1252 xfer_size = i2c_dev->msg_len + I2C_PACKET_HEADER_SIZE;
1256 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN &&
1257 i2c_dev->dma_buf && !i2c_dev->atomic_mode;
1259 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1266 i2c_dev->timings.bus_freq_hz);
1269 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1271 if (i2c_dev->dma_mode) {
1272 if (i2c_dev->msg_read) {
1273 dma_sync_single_for_device(i2c_dev->dma_dev,
1274 i2c_dev->dma_phys,
1277 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1281 dma_sync_single_for_cpu(i2c_dev->dma_dev,
1282 i2c_dev->dma_phys,
1287 tegra_i2c_push_packet_header(i2c_dev, msg, end_state);
1289 if (!i2c_dev->msg_read) {
1290 if (i2c_dev->dma_mode) {
1291 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE,
1292 msg->buf, i2c_dev->msg_len);
1294 dma_sync_single_for_device(i2c_dev->dma_dev,
1295 i2c_dev->dma_phys,
1298 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1302 tegra_i2c_fill_tx_fifo(i2c_dev);
1306 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1309 if (!i2c_dev->dma_mode) {
1312 else if (i2c_dev->msg_buf_remaining)
1316 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1317 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n",
1318 i2c_readl(i2c_dev, I2C_INT_MASK));
1320 if (i2c_dev->dma_mode) {
1321 time_left = tegra_i2c_wait_completion(i2c_dev,
1322 &i2c_dev->dma_complete,
1330 dmaengine_synchronize(i2c_dev->dma_chan);
1331 dmaengine_terminate_sync(i2c_dev->dma_chan);
1333 if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
1334 dev_err(i2c_dev->dev, "DMA transfer timed out\n");
1335 tegra_i2c_init(i2c_dev);
1339 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
1340 dma_sync_single_for_cpu(i2c_dev->dma_dev,
1341 i2c_dev->dma_phys,
1344 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len);
1348 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete,
1351 tegra_i2c_mask_irq(i2c_dev, int_mask);
1354 dev_err(i2c_dev->dev, "I2C transfer timed out\n");
1355 tegra_i2c_init(i2c_dev);
1359 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1360 time_left, completion_done(&i2c_dev->msg_complete),
1361 i2c_dev->msg_err);
1363 i2c_dev->dma_mode = false;
1365 err = tegra_i2c_error_recover(i2c_dev, msg);
1375 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1378 ret = pm_runtime_get_sync(i2c_dev->dev);
1380 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1381 pm_runtime_put_noidle(i2c_dev->dev);
1397 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE);
1402 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len);
1404 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1409 pm_runtime_put(i2c_dev->dev);
1417 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1420 i2c_dev->atomic_mode = true;
1422 i2c_dev->atomic_mode = false;
1429 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1433 if (i2c_dev->hw->has_continue_xfer_support)
1647 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1649 struct device_node *np = i2c_dev->dev->of_node;
1652 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true);
1654 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master");
1655 i2c_dev->multimaster_mode = multi_mode;
1659 i2c_dev->is_dvc = true;
1663 i2c_dev->is_vi = true;
1666 static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev)
1668 if (ACPI_HANDLE(i2c_dev->dev))
1671 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c");
1672 if (IS_ERR(i2c_dev->rst))
1673 return dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst),
1679 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)
1683 if (ACPI_HANDLE(i2c_dev->dev))
1686 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk";
1688 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw)
1689 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk";
1691 if (IS_VI(i2c_dev))
1692 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow";
1694 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks,
1695 i2c_dev->clocks);
1699 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks);
1703 i2c_dev->div_clk = i2c_dev->clocks[0].clk;
1705 if (!i2c_dev->multimaster_mode)
1708 err = clk_enable(i2c_dev->div_clk);
1710 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err);
1717 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1722 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev)
1724 if (i2c_dev->multimaster_mode)
1725 clk_disable(i2c_dev->div_clk);
1727 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1730 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev)
1734 ret = pm_runtime_get_sync(i2c_dev->dev);
1736 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret);
1738 ret = tegra_i2c_init(i2c_dev);
1740 pm_runtime_put_sync(i2c_dev->dev);
1747 struct tegra_i2c_dev *i2c_dev;
1751 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1752 if (!i2c_dev)
1755 platform_set_drvdata(pdev, i2c_dev);
1757 init_completion(&i2c_dev->msg_complete);
1758 init_completion(&i2c_dev->dma_complete);
1760 i2c_dev->hw = device_get_match_data(&pdev->dev);
1761 i2c_dev->cont_id = pdev->id;
1762 i2c_dev->dev = &pdev->dev;
1764 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1765 if (IS_ERR(i2c_dev->base))
1766 return PTR_ERR(i2c_dev->base);
1768 i2c_dev->base_phys = res->start;
1774 i2c_dev->irq = err;
1777 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
1779 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq,
1782 dev_name(i2c_dev->dev), i2c_dev);
1786 tegra_i2c_parse_dt(i2c_dev);
1788 err = tegra_i2c_init_reset(i2c_dev);
1792 err = tegra_i2c_init_clocks(i2c_dev);
1796 err = tegra_i2c_init_dma(i2c_dev);
1809 if (!IS_VI(i2c_dev))
1810 pm_runtime_irq_safe(i2c_dev->dev);
1812 pm_runtime_enable(i2c_dev->dev);
1814 err = tegra_i2c_init_hardware(i2c_dev);
1818 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1819 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node;
1820 i2c_dev->adapter.dev.parent = i2c_dev->dev;
1821 i2c_dev->adapter.retries = 1;
1822 i2c_dev->adapter.timeout = 6 * HZ;
1823 i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1824 i2c_dev->adapter.owner = THIS_MODULE;
1825 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1826 i2c_dev->adapter.algo = &tegra_i2c_algo;
1827 i2c_dev->adapter.nr = pdev->id;
1828 ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev));
1830 if (i2c_dev->hw->supports_bus_clear)
1831 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1833 strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
1834 sizeof(i2c_dev->adapter.name));
1836 err = i2c_add_numbered_adapter(&i2c_dev->adapter);
1843 pm_runtime_disable(i2c_dev->dev);
1845 tegra_i2c_release_dma(i2c_dev);
1847 tegra_i2c_release_clocks(i2c_dev);
1854 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1856 i2c_del_adapter(&i2c_dev->adapter);
1857 pm_runtime_force_suspend(i2c_dev->dev);
1859 tegra_i2c_release_dma(i2c_dev);
1860 tegra_i2c_release_clocks(i2c_dev);
1865 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1872 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks);
1881 if (IS_VI(i2c_dev)) {
1882 err = tegra_i2c_init(i2c_dev);
1890 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
1897 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1899 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
1906 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1909 i2c_mark_adapter_suspended(&i2c_dev->adapter);
1922 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1933 err = tegra_i2c_init(i2c_dev);
1948 i2c_mark_adapter_resumed(&i2c_dev->adapter);