Lines Matching refs:cr2
187 * @cr2: Control register 2
194 u32 cr2;
796 u32 cr2;
801 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
803 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
805 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
807 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
808 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
811 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
817 u32 cr2;
831 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
832 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
833 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
834 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
869 u32 cr1, cr2;
881 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
884 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
886 cr2 |= STM32F7_I2C_CR2_RD_WRN;
889 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
891 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
892 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
893 cr2 |= STM32F7_I2C_CR2_ADD10;
895 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
896 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
900 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
902 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
903 cr2 |= STM32F7_I2C_CR2_RELOAD;
905 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
943 cr2 |= STM32F7_I2C_CR2_START;
949 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
959 u32 cr1, cr2;
965 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
969 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
971 cr2 |= STM32F7_I2C_CR2_RD_WRN;
974 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
975 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
991 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1002 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1014 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1033 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1046 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1063 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1068 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1072 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1073 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1087 cr2 & STM32F7_I2C_CR2_RD_WRN,
1098 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1103 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1110 cr2 |= STM32F7_I2C_CR2_START;
1116 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1125 u32 cr1, cr2;
1128 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1132 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1145 cr2 |= STM32F7_I2C_CR2_RELOAD;
1154 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1159 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1160 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1181 cr2 & STM32F7_I2C_CR2_RD_WRN,
1198 cr2 |= STM32F7_I2C_CR2_START;
1202 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1419 u32 cr2, status, mask;
1446 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1447 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1448 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
2385 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2417 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);