Lines Matching refs:se
17 #include <linux/soc/qcom/geni-se.h>
81 struct geni_se se;
174 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
177 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
182 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
187 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
188 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
189 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
190 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
191 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
195 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
196 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
198 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
199 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
201 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
203 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
212 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
221 dev_dbg(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
224 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
233 void __iomem *base = gi2c->se.base;
273 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
339 geni_se_abort_m_cmd(&gi2c->se);
347 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
355 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
358 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
362 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
370 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
373 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
377 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
387 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
399 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
410 struct geni_se *se = &gi2c->se;
416 geni_se_select_mode(se, GENI_SE_DMA);
418 geni_se_select_mode(se, GENI_SE_FIFO);
420 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
421 geni_se_setup_m_cmd(se, I2C_READ, m_param);
423 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
424 geni_se_select_mode(se, GENI_SE_FIFO);
449 struct geni_se *se = &gi2c->se;
455 geni_se_select_mode(se, GENI_SE_DMA);
457 geni_se_select_mode(se, GENI_SE_FIFO);
459 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
460 geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
462 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
463 geni_se_select_mode(se, GENI_SE_FIFO);
473 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
490 dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result);
493 dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue);
504 dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE);
509 dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE);
538 addr = dma_map_single(gi2c->se.dev->parent, dma_buf, msg->len, map_dirn);
539 if (dma_mapping_error(gi2c->se.dev->parent, addr)) {
550 dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op);
565 dev_err(gi2c->se.dev, "prep_slave_sg failed\n");
580 dma_unmap_single(gi2c->se.dev->parent, addr, msg->len, map_dirn);
608 dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len);
634 dev_err(gi2c->se.dev, "I2C timeout gpi flags:%d addr:0x%x\n",
650 dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret);
689 ret = pm_runtime_get_sync(gi2c->se.dev);
691 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
692 pm_runtime_put_noidle(gi2c->se.dev);
694 pm_runtime_set_suspended(gi2c->se.dev);
705 pm_runtime_mark_last_busy(gi2c->se.dev);
706 pm_runtime_put_autosuspend(gi2c->se.dev);
743 geni_se_select_mode(&gi2c->se, GENI_GPI_DMA);
744 gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx");
746 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c),
751 gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx");
753 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c),
758 dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n");
779 gi2c->se.dev = dev;
780 gi2c->se.wrapper = dev_get_drvdata(dev->parent);
781 gi2c->se.base = devm_platform_ioremap_resource(pdev, 0);
782 if (IS_ERR(gi2c->se.base))
783 return PTR_ERR(gi2c->se.base);
793 gi2c->se.clk = devm_clk_get(dev, "se");
794 if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev))
795 return PTR_ERR(gi2c->se.clk);
836 ret = geni_icc_get(&gi2c->se, desc ? desc->icc_ddr : "qup-memory");
844 gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
845 gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
847 gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out);
849 ret = geni_icc_set_bw(&gi2c->se);
857 ret = geni_se_resources_on(&gi2c->se);
863 proto = geni_se_read_proto(&gi2c->se);
866 geni_se_resources_off(&gi2c->se);
874 fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
881 geni_se_resources_off(&gi2c->se);
889 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
897 geni_se_resources_off(&gi2c->se);
903 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
904 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE,
907 dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
911 ret = geni_se_resources_off(&gi2c->se);
917 ret = geni_icc_disable(&gi2c->se);
922 pm_runtime_set_suspended(gi2c->se.dev);
923 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
924 pm_runtime_use_autosuspend(gi2c->se.dev);
925 pm_runtime_enable(gi2c->se.dev);
930 pm_runtime_disable(gi2c->se.dev);
949 pm_runtime_disable(gi2c->se.dev);
966 ret = geni_se_resources_off(&gi2c->se);
977 return geni_icc_disable(&gi2c->se);
985 ret = geni_icc_enable(&gi2c->se);
993 ret = geni_se_resources_on(&gi2c->se);