Lines Matching defs:queue
295 static int cci_run_queue(struct cci *cci, u8 master, u8 queue)
299 val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
300 writel(val, cci->base + CCI_I2C_Mm_Qn_EXEC_WORD_CNT(master, queue));
303 val = BIT(master * 2 + queue);
308 dev_err(cci->dev, "master %d queue %d timeout\n",
309 master, queue);
318 static int cci_validate_queue(struct cci *cci, u8 master, u8 queue)
322 val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
323 if (val == cci->data->queue_size[queue])
330 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
332 return cci_run_queue(cci, master, queue);
339 u8 queue = QUEUE_1;
344 * Call validate queue to make sure queue is empty before starting.
345 * This is to avoid overflow / underflow of queue.
347 ret = cci_validate_queue(cci, master, queue);
352 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
355 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
357 ret = cci_run_queue(cci, master, queue);
391 u8 queue = QUEUE_0;
397 * Call validate queue to make sure queue is empty before starting.
398 * This is to avoid overflow / underflow of queue.
400 ret = cci_validate_queue(cci, master, queue);
405 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
417 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
421 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
423 return cci_run_queue(cci, master, queue);