Lines Matching defs:i2c
24 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-pxa.h>
112 * 7 GCD 1 (Disables i2c unit response to general call messages as a slave)
114 * 5 SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
206 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
209 { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
215 { "pxa2xx-i2c", REGS_PXA2XX },
217 { "ce4100-i2c", REGS_CE4100 },
218 { "pxa910-i2c", REGS_PXA910 },
219 { "armada-3700-i2c", REGS_A3700 },
272 #define _IBMR(i2c) ((i2c)->reg_ibmr)
273 #define _IDBR(i2c) ((i2c)->reg_idbr)
274 #define _ICR(i2c) ((i2c)->reg_icr)
275 #define _ISR(i2c) ((i2c)->reg_isr)
276 #define _ISAR(i2c) ((i2c)->reg_isar)
277 #define _ILCR(i2c) ((i2c)->reg_ilcr)
278 #define _IWCR(i2c) ((i2c)->reg_iwcr)
353 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
355 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
356 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
359 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
361 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
364 struct device *dev = &i2c->adap.dev;
367 i2c->req_slave_addr >> 1, why);
369 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
371 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
372 readl(_ISR(i2c)));
374 for (i = 0; i < i2c->irqlogidx; i++)
375 pr_cont(" [%03x:%05x]", i2c->isrlog[i], i2c->icrlog[i]);
383 #define show_state(i2c) do { } while (0)
386 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
390 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
392 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
394 return !(readl(_ICR(i2c)) & ICR_SCLE);
397 static void i2c_pxa_abort(struct pxa_i2c *i2c)
401 if (i2c_pxa_is_slavemode(i2c)) {
402 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
406 while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) {
407 unsigned long icr = readl(_ICR(i2c));
412 writel(icr, _ICR(i2c));
414 show_state(i2c);
420 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
421 _ICR(i2c));
424 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
430 isr = readl(_ISR(i2c));
441 show_state(i2c);
444 show_state(i2c);
449 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
455 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
456 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
458 if (readl(_ISR(i2c)) & ISR_SAD) {
460 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
465 * quick check of the i2c lines themselves to ensure they've
468 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 &&
469 readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) {
471 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
479 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
484 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
487 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
489 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
490 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
491 if (!i2c_pxa_wait_master(i2c)) {
492 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
497 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
502 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
508 show_state(i2c);
512 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
513 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
515 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
516 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
517 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
519 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
527 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
535 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
537 show_state(i2c);
545 if (readl(_ICR(i2c)) & ICR_STOP) {
547 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
550 if (!i2c_pxa_wait_slave(i2c)) {
551 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
557 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
558 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
561 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
562 decode_ICR(readl(_ICR(i2c)));
566 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
569 static void i2c_pxa_do_reset(struct pxa_i2c *i2c)
572 writel(ICR_UR, _ICR(i2c));
573 writel(I2C_ISR_INIT, _ISR(i2c));
574 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
576 if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
577 writel(i2c->slave_addr, _ISAR(i2c));
580 writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
581 writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
584 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
585 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
588 i2c_pxa_set_slave(i2c, 0);
591 static void i2c_pxa_enable(struct pxa_i2c *i2c)
594 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
598 static void i2c_pxa_reset(struct pxa_i2c *i2c)
603 i2c_pxa_abort(i2c);
604 i2c_pxa_do_reset(i2c);
605 i2c_pxa_enable(i2c);
614 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
621 if (i2c->slave != NULL)
622 i2c_slave_event(i2c->slave, I2C_SLAVE_READ_PROCESSED,
625 writel(byte, _IDBR(i2c));
626 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
630 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
632 u8 byte = readl(_IDBR(i2c));
634 if (i2c->slave != NULL)
635 i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_RECEIVED, &byte);
637 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
640 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
645 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
648 if (i2c->slave != NULL) {
652 i2c_slave_event(i2c->slave, I2C_SLAVE_READ_REQUESTED,
654 writel(byte, _IDBR(i2c));
656 i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_REQUESTED,
666 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
667 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
672 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
678 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
683 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
686 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
689 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
691 if (i2c->slave != NULL)
692 i2c_slave_event(i2c->slave, I2C_SLAVE_STOP, NULL);
695 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
701 if (i2c->msg)
702 i2c_pxa_master_complete(i2c, I2C_RETRY);
707 struct pxa_i2c *i2c = slave->adapter->algo_data;
709 if (i2c->slave)
712 if (!i2c->reg_isar)
715 i2c->slave = slave;
716 i2c->slave_addr = slave->addr;
718 writel(i2c->slave_addr, _ISAR(i2c));
725 struct pxa_i2c *i2c = slave->adapter->algo_data;
727 WARN_ON(!i2c->slave);
729 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
730 writel(i2c->slave_addr, _ISAR(i2c));
732 i2c->slave = NULL;
737 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
742 writel(0, _IDBR(i2c));
743 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
747 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
749 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
752 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
761 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
762 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
767 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
773 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
778 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
781 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
783 if (i2c->msg)
784 i2c_pxa_master_complete(i2c, I2C_RETRY);
792 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
799 i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
800 writel(i2c->req_slave_addr, _IDBR(i2c));
805 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
806 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
809 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
814 icr = readl(_ICR(i2c));
816 writel(icr, _ICR(i2c));
825 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
830 spin_lock_irq(&i2c->lock);
831 i2c->highmode_enter = true;
832 writel(i2c->master_code, _IDBR(i2c));
834 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
836 writel(icr, _ICR(i2c));
838 spin_unlock_irq(&i2c->lock);
839 timeout = wait_event_timeout(i2c->wait,
840 i2c->highmode_enter == false, HZ * 1);
842 i2c->highmode_enter = false;
850 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
852 i2c->msg_ptr = 0;
853 i2c->msg = NULL;
854 i2c->msg_idx ++;
855 i2c->msg_num = 0;
857 i2c->msg_idx = ret;
858 if (!i2c->use_pio)
859 wake_up(&i2c->wait);
862 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
864 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
875 i2c_pxa_scream_blue_murder(i2c, "ALD set");
887 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
897 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
902 i2c_pxa_master_complete(i2c, ret);
908 if (i2c->msg_ptr == i2c->msg->len - 1 &&
909 i2c->msg_idx == i2c->msg_num - 1)
913 } else if (i2c->msg_ptr < i2c->msg->len) {
917 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
925 if ((i2c->msg_ptr == i2c->msg->len) &&
926 ((i2c->msg->flags & I2C_M_STOP) ||
927 (i2c->msg_idx == i2c->msg_num - 1)))
930 } else if (i2c->msg_idx < i2c->msg_num - 1) {
934 i2c->msg_ptr = 0;
935 i2c->msg_idx ++;
936 i2c->msg++;
943 if (i2c->msg->flags & I2C_M_NOSTART)
949 i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
950 writel(i2c->req_slave_addr, _IDBR(i2c));
958 if (i2c->msg->len == 0)
960 i2c_pxa_master_complete(i2c, 0);
963 i2c->icrlog[i2c->irqlogidx-1] = icr;
965 writel(icr, _ICR(i2c));
966 show_state(i2c);
969 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
971 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
976 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
978 if (i2c->msg_ptr < i2c->msg->len) {
983 if (i2c->msg_ptr == i2c->msg->len - 1)
988 i2c_pxa_master_complete(i2c, 0);
991 i2c->icrlog[i2c->irqlogidx-1] = icr;
993 writel(icr, _ICR(i2c));
1000 struct pxa_i2c *i2c = dev_id;
1001 u32 isr = readl(_ISR(i2c));
1007 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1008 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1012 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1013 i2c->isrlog[i2c->irqlogidx++] = isr;
1015 show_state(i2c);
1020 writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1023 i2c_pxa_slave_start(i2c, isr);
1025 i2c_pxa_slave_stop(i2c);
1027 if (i2c_pxa_is_slavemode(i2c)) {
1029 i2c_pxa_slave_txempty(i2c, isr);
1031 i2c_pxa_slave_rxfull(i2c, isr);
1032 } else if (i2c->msg && (!i2c->highmode_enter)) {
1034 i2c_pxa_irq_txempty(i2c, isr);
1036 i2c_pxa_irq_rxfull(i2c, isr);
1037 } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1038 i2c->highmode_enter = false;
1039 wake_up(&i2c->wait);
1041 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1050 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
1058 ret = i2c_pxa_wait_bus_not_busy(i2c);
1060 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
1061 i2c_recover_bus(&i2c->adap);
1068 ret = i2c_pxa_set_master(i2c);
1070 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
1074 if (i2c->high_mode) {
1075 ret = i2c_pxa_send_mastercode(i2c);
1077 dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
1082 spin_lock_irq(&i2c->lock);
1084 i2c->msg = msg;
1085 i2c->msg_num = num;
1086 i2c->msg_idx = 0;
1087 i2c->msg_ptr = 0;
1088 i2c->irqlogidx = 0;
1090 i2c_pxa_start_message(i2c);
1092 spin_unlock_irq(&i2c->lock);
1097 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
1098 i2c_pxa_stop_message(i2c);
1101 * We place the return code in i2c->msg_idx.
1103 ret = i2c->msg_idx;
1105 if (!timeout && i2c->msg_num) {
1106 i2c_pxa_scream_blue_murder(i2c, "timeout with active message");
1107 i2c_recover_bus(&i2c->adap);
1115 static int i2c_pxa_internal_xfer(struct pxa_i2c *i2c,
1123 ret = xfer(i2c, msgs, num);
1126 if (++i >= i2c->adap.retries)
1130 dev_dbg(&i2c->adap.dev, "Retrying transmission\n");
1134 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1137 i2c_pxa_set_slave(i2c, ret);
1144 struct pxa_i2c *i2c = adap->algo_data;
1146 return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_xfer);
1165 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
1173 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB))
1177 show_state(i2c);
1178 dev_err(&i2c->adap.dev,
1186 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
1191 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
1197 ret = i2c_pxa_pio_set_master(i2c);
1201 i2c->msg = msg;
1202 i2c->msg_num = num;
1203 i2c->msg_idx = 0;
1204 i2c->msg_ptr = 0;
1205 i2c->irqlogidx = 0;
1207 i2c_pxa_start_message(i2c);
1209 while (i2c->msg_num > 0 && --timeout) {
1210 i2c_pxa_handler(0, i2c);
1214 i2c_pxa_stop_message(i2c);
1217 * We place the return code in i2c->msg_idx.
1219 ret = i2c->msg_idx;
1223 i2c_pxa_scream_blue_murder(i2c, "timeout (do_pio_xfer)");
1233 struct pxa_i2c *i2c = adap->algo_data;
1239 if (!(readl(_ICR(i2c)) & ICR_IUE))
1240 i2c_pxa_reset(i2c);
1242 return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_pio_xfer);
1254 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1265 i2c->adap.nr = -1;
1267 i2c->use_pio = of_property_read_bool(np, "mrvl,i2c-polling");
1268 i2c->fast_mode = of_property_read_bool(np, "mrvl,i2c-fast-mode");
1276 struct pxa_i2c *i2c,
1284 i2c->use_pio = plat->use_pio;
1285 i2c->fast_mode = plat->fast_mode;
1286 i2c->high_mode = plat->high_mode;
1287 i2c->master_code = plat->master_code;
1288 if (!i2c->master_code)
1289 i2c->master_code = 0xe;
1290 i2c->rate = plat->rate;
1297 struct pxa_i2c *i2c = adap->algo_data;
1298 u32 ibmr = readl(_IBMR(i2c));
1304 gpiod_set_value(i2c->recovery.scl_gpiod, ibmr & IBMR_SCLS);
1305 gpiod_set_value(i2c->recovery.sda_gpiod, ibmr & IBMR_SDAS);
1307 WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery));
1312 struct pxa_i2c *i2c = adap->algo_data;
1319 isr = readl(_ISR(i2c));
1321 dev_dbg(&i2c->adap.dev,
1323 i2c_pxa_do_reset(i2c);
1326 WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default));
1328 dev_dbg(&i2c->adap.dev, "recovery: IBMR 0x%08x ISR 0x%08x\n",
1329 readl(_IBMR(i2c)), readl(_ISR(i2c)));
1331 i2c_pxa_enable(i2c);
1334 static int i2c_pxa_init_recovery(struct pxa_i2c *i2c)
1336 struct i2c_bus_recovery_info *bri = &i2c->recovery;
1337 struct device *dev = i2c->adap.dev.parent;
1348 i2c->pinctrl = devm_pinctrl_get(dev);
1349 if (PTR_ERR(i2c->pinctrl) == -ENODEV)
1350 i2c->pinctrl = NULL;
1351 if (IS_ERR(i2c->pinctrl))
1352 return PTR_ERR(i2c->pinctrl);
1354 if (!i2c->pinctrl)
1357 i2c->pinctrl_default = pinctrl_lookup_state(i2c->pinctrl,
1359 i2c->pinctrl_recovery = pinctrl_lookup_state(i2c->pinctrl, "recovery");
1361 if (IS_ERR(i2c->pinctrl_default) || IS_ERR(i2c->pinctrl_recovery)) {
1363 PTR_ERR(i2c->pinctrl_default),
1364 PTR_ERR(i2c->pinctrl_recovery));
1406 i2c->adap.bus_recovery_info = bri;
1415 pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery);
1417 return pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default);
1424 struct pxa_i2c *i2c;
1428 i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1429 if (!i2c)
1433 i2c->adap.nr = dev->id;
1434 i2c->adap.owner = THIS_MODULE;
1435 i2c->adap.retries = 5;
1436 i2c->adap.algo_data = i2c;
1437 i2c->adap.dev.parent = &dev->dev;
1439 i2c->adap.dev.of_node = dev->dev.of_node;
1442 i2c->reg_base = devm_platform_get_and_ioremap_resource(dev, 0, &res);
1443 if (IS_ERR(i2c->reg_base))
1444 return PTR_ERR(i2c->reg_base);
1450 ret = i2c_pxa_init_recovery(i2c);
1454 ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1456 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1460 spin_lock_init(&i2c->lock);
1461 init_waitqueue_head(&i2c->wait);
1463 strscpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1465 i2c->clk = devm_clk_get(&dev->dev, NULL);
1466 if (IS_ERR(i2c->clk))
1467 return dev_err_probe(&dev->dev, PTR_ERR(i2c->clk),
1470 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1471 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1472 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1473 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1474 i2c->fm_mask = pxa_reg_layout[i2c_type].fm;
1475 i2c->hs_mask = pxa_reg_layout[i2c_type].hs;
1478 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1481 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
1482 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
1485 i2c->iobase = res->start;
1486 i2c->iosize = resource_size(res);
1488 i2c->irq = irq;
1490 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1491 i2c->highmode_enter = false;
1494 i2c->adap.class = plat->class;
1497 if (i2c->high_mode) {
1498 if (i2c->rate) {
1499 clk_set_rate(i2c->clk, i2c->rate);
1500 pr_info("i2c: <%s> set rate to %ld\n",
1501 i2c->adap.name, clk_get_rate(i2c->clk));
1503 pr_warn("i2c: <%s> clock rate not set\n",
1504 i2c->adap.name);
1507 clk_prepare_enable(i2c->clk);
1509 if (i2c->use_pio) {
1510 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1512 i2c->adap.algo = &i2c_pxa_algorithm;
1515 dev_name(&dev->dev), i2c);
1522 i2c_pxa_reset(i2c);
1524 ret = i2c_add_numbered_adapter(&i2c->adap);
1528 platform_set_drvdata(dev, i2c);
1531 dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1532 i2c->slave_addr);
1534 dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1539 clk_disable_unprepare(i2c->clk);
1545 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1547 i2c_del_adapter(&i2c->adap);
1549 clk_disable_unprepare(i2c->clk);
1554 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1556 clk_disable(i2c->clk);
1563 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1565 clk_enable(i2c->clk);
1566 i2c_pxa_reset(i2c);
1580 .name = "pxa2xx-i2c",