Lines Matching refs:i2c_dev
121 static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
123 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
126 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
130 writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
133 static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev)
138 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
144 val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
151 dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n");
158 static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
162 val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16);
165 writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
168 static void owl_i2c_xfer_data(struct owl_i2c_dev *i2c_dev)
170 struct i2c_msg *msg = i2c_dev->msg;
173 i2c_dev->err = 0;
176 fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
178 i2c_dev->err = -ENXIO;
180 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOSTAT,
186 stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
188 i2c_dev->err = -EIO;
190 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
197 while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
198 OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) {
199 msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
204 while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
205 OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) {
206 writel(msg->buf[i2c_dev->msg_ptr++],
207 i2c_dev->base + OWL_I2C_REG_TXDAT);
214 struct owl_i2c_dev *i2c_dev = _dev;
216 spin_lock(&i2c_dev->lock);
218 owl_i2c_xfer_data(i2c_dev);
221 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
224 complete_all(&i2c_dev->msg_complete);
225 spin_unlock(&i2c_dev->lock);
237 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
242 while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) {
255 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
262 spin_lock_irqsave(&i2c_dev->lock, flags);
265 owl_i2c_reset(i2c_dev);
268 owl_i2c_set_freq(i2c_dev);
274 spin_unlock_irqrestore(&i2c_dev->lock, flags);
277 ret = owl_i2c_reset_fifo(i2c_dev);
286 spin_lock_irqsave(&i2c_dev->lock, flags);
289 val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
292 writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
298 reinit_completion(&i2c_dev->msg_complete);
301 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
319 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
324 i2c_dev->base + OWL_I2C_REG_TXDAT);
333 i2c_dev->msg = msg;
334 i2c_dev->msg_ptr = 0;
337 writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
340 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
346 if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
351 i2c_dev->base + OWL_I2C_REG_TXDAT);
354 i2c_dev->msg_ptr = idx;
359 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
362 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
366 writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
368 spin_unlock_irqrestore(&i2c_dev->lock, flags);
372 ret = readl_poll_timeout_atomic(i2c_dev->base + OWL_I2C_REG_FIFOSTAT,
377 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
383 spin_lock_irqsave(&i2c_dev->lock, flags);
388 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
395 owl_i2c_xfer_data(i2c_dev);
397 ret = i2c_dev->err < 0 ? i2c_dev->err : num;
400 spin_unlock_irqrestore(&i2c_dev->lock, flags);
404 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
439 struct owl_i2c_dev *i2c_dev;
442 i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
443 if (!i2c_dev)
446 i2c_dev->base = devm_platform_ioremap_resource(pdev, 0);
447 if (IS_ERR(i2c_dev->base))
448 return PTR_ERR(i2c_dev->base);
455 &i2c_dev->bus_freq))
456 i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
459 if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ &&
460 i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ) {
461 dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
465 i2c_dev->clk = devm_clk_get_enabled(dev, NULL);
466 if (IS_ERR(i2c_dev->clk)) {
468 return PTR_ERR(i2c_dev->clk);
471 i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
472 if (!i2c_dev->clk_rate) {
477 init_completion(&i2c_dev->msg_complete);
478 spin_lock_init(&i2c_dev->lock);
479 i2c_dev->adap.owner = THIS_MODULE;
480 i2c_dev->adap.algo = &owl_i2c_algorithm;
481 i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
482 i2c_dev->adap.quirks = &owl_i2c_quirks;
483 i2c_dev->adap.dev.parent = dev;
484 i2c_dev->adap.dev.of_node = dev->of_node;
485 snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
487 i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
489 platform_set_drvdata(pdev, i2c_dev);
492 i2c_dev);
498 return i2c_add_adapter(&i2c_dev->adap);